JPH0434059U - - Google Patents

Info

Publication number
JPH0434059U
JPH0434059U JP7466290U JP7466290U JPH0434059U JP H0434059 U JPH0434059 U JP H0434059U JP 7466290 U JP7466290 U JP 7466290U JP 7466290 U JP7466290 U JP 7466290U JP H0434059 U JPH0434059 U JP H0434059U
Authority
JP
Japan
Prior art keywords
output
light
block
receiving element
reading device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7466290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7466290U priority Critical patent/JPH0434059U/ja
Publication of JPH0434059U publication Critical patent/JPH0434059U/ja
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Facsimile Heads (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の読み取り装置の一実施例の
概略を説明するための回路図、第2図は、第1図
の出力信号の説明図、第3図乃至第5図は、第1
図の読み出し回路用いた異なる実施例のブロツク
図、第6図は、読み出し回路のICの説明図、第
7図、第8図は、従来の読み取り装置の一例の概
略を説明するための回路図である。 1……読み出し回路、2……A/D変換回路、
3……第1のシフトレジスタ、4……第2のシフ
トレジスタ、5……タイミング調整回路、6……
マルチプレクサ、OUT……出力端子。
FIG. 1 is a circuit diagram for explaining the outline of one embodiment of the reading device of the present invention, FIG. 2 is an explanatory diagram of the output signal of FIG. 1, and FIGS.
6 is an explanatory diagram of the IC of the readout circuit, and FIGS. 7 and 8 are circuit diagrams for explaining the outline of an example of a conventional reading device. It is. 1... Readout circuit, 2... A/D conversion circuit,
3...First shift register, 4...Second shift register, 5...Timing adjustment circuit, 6...
Multiplexer, OUT...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の受光素子を1ブロツクとして複数ブロツ
クよりなる受光素子アレイと、前記受光素子で発
生した電荷をブロツクごとに出力回路へ転送する
スイツチング素子とを有し、これらスイツチング
素子がブロツクごとに選択され、かつ、隣合うブ
ロツクの出力回路における順位が逆方向となるよ
う共通に接続されて、出力回路の出力がスイツチ
ング素子の選択に同期した選択回路により選択さ
れる読み取り装置において、前記選択回路よりの
出力信号をデジタル信号に変換した後、シフトレ
ジスタを用いて、受光素子アレイに対して、時系
列的な出力を得るようにしたことを特徴とする読
み取り装置。
It has a light-receiving element array consisting of a plurality of blocks each including a plurality of light-receiving elements, and a switching element that transfers the charge generated in the light-receiving element to an output circuit block by block, and these switching elements are selected for each block, In a reading device in which adjacent blocks are commonly connected so that the order in the output circuits is reversed, and the output of the output circuit is selected by a selection circuit synchronized with the selection of the switching element, the output from the selection circuit is A reading device characterized in that, after converting a signal into a digital signal, a shift register is used to obtain a time-series output to a light receiving element array.
JP7466290U 1990-07-14 1990-07-14 Pending JPH0434059U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7466290U JPH0434059U (en) 1990-07-14 1990-07-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7466290U JPH0434059U (en) 1990-07-14 1990-07-14

Publications (1)

Publication Number Publication Date
JPH0434059U true JPH0434059U (en) 1992-03-19

Family

ID=31614549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7466290U Pending JPH0434059U (en) 1990-07-14 1990-07-14

Country Status (1)

Country Link
JP (1) JPH0434059U (en)

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