JPH04346514A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To obtain an emitter follower circuit which can reduce a Circuit layout area together with reduction of the power consumption and furthermore can output a stable binary logical signal together with improvement of the operating speed. CONSTITUTION:An input signal Vin is inputted to the base of an npn transistor Tr1 connected to a high potential power supply Vcc through its collector. A binary logical signal having the same phase as the input signal Vin received from the emitter of the TR1 is outputted as an output signal Vout. The emitter of the Tr1 is connected to a low potential power supply VEE via a load and a current source 1. Thus an emitter follower circuit is obtained. The load of a semiconductor logic circuit where many emitter follower circuits are connected in parallel consists of a MOS Tr2 which is always kept turned on with the gate voltage of a fixed level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit used in a decoder or the like in a semiconductor memory device. In some semiconductor memory devices, the decoder is constructed from a semiconductor logic circuit including a large number of emitter follower circuits. In recent years, as semiconductor memory devices have increased in capacity, the scale of their decoders has also increased, so it has become necessary to ensure that the emitter follower circuits that make up the decoders operate reliably while reducing their power consumption.

0002

2. Description of the Related Art The basic circuit of an emitter follower circuit used in a decoder in a semiconductor memory device will be described with reference to FIG. An input signal Vin, which is an L-level binary logic signal, is input, and the emitter is connected to the output terminal Tout as well as to the low potential power supply VEE via the current source 1. When the H level input signal Vin is input, the level is shifted by the transistor Tr1 and the H level output signal Vout is output from the output terminal Tout, and when the L level input signal Vin is input, the emitter of the transistor Tr1 is output. The accumulated charge at the output terminal Tout is absorbed by the current source 1, and the output signal Vout becomes L.
be lowered to the level.

If a decoder is constructed by arranging, for example, 10 such emitter follower circuits in parallel, and each emitter follower circuit is operated by flowing a current of 1 mA, the entire decoder consumes 10 mA of current, reducing power consumption. As the size increases, it is necessary to provide a current source 1 for each emitter follower circuit, which requires a large area in the circuit layout.

Therefore, in order to reduce this current consumption, as shown in FIG. 5, the current source 1 of each emitter follower circuit is made common, and the transistor Tr1 of each emitter follower circuit is
A decoder is constructed in which a resistor R is connected as a load between the emitter of the circuit and the current source 1, and a current of 1 mA is passed through each emitter follower circuit when an H level is output.
When configured to flow a current of 0.1 mA when outputting L level, the decoder normally outputs the output signals Vout1 to Vout.
At the same time that any one of n goes to H level, the other output signals go to L level, so if a decoder is configured by connecting 10 emitter follower circuits in parallel as above, the consumption will be reduced. It becomes possible to suppress the current to 1.9 mA and reduce power consumption.

However, in the emitter follower circuit as shown in FIG. 5, the load of the transistor Tr1 is constituted by a resistor R, and the low potential terminal voltage Va of the resistor R is maintained constant by the current source 1, so that the output Signal Vo
As the potential of ut decreases, the current value absorbed by the current source 1 from the output terminal Tout via the resistor R decreases. Therefore, there is a problem that the fall of the output signal Vout from the H level to the L level is slow, resulting in a decrease in operating speed. Therefore, if an attempt is made to increase the falling speed of the output signal Vout by increasing the current capacity of the current source 1, the relative resistance value of the current source 1 to the resistor R decreases, and the voltage at the low potential side terminal of the resistor R decreases. Since Va decreases, the terminal voltage Va decreases due to voltage fluctuations in the power supply Vcc.
If the difference between V and the power supply VEE becomes small, the operation of the current source 1 becomes unstable, which causes the problem that the output signal Vout becomes unstable.

Therefore, as shown in FIG. 7, a decoder has been proposed in which, in place of the resistor R, an emitter follower circuit with a diode D as a load is connected in parallel. In such a decoder, even if the difference between the output signal Vout and the cathode terminal voltage Vb of the diode D becomes small, a relatively large current flows through the current source 1. Therefore, compared to the decoder shown in FIG. The falling speed can be improved.

[0007]

However, in the decoder shown in FIG. 7, when the amplitude of the input signals Vin1 to Vinn increases, the level of the output signal Vout of the transistor Tr1, one of which is an H level input, increases.
Since the cathode side terminal voltage Vb of each diode D rises due to the output signal Vout, there is a problem that the falling speed of the output signal Vout which attempts to shift to another L level decreases. In addition, the input signal Vin1
When ~Vinn switches, for example, the current capacity is transferred to the current source 1 from the emitter follower circuit that transitions from the H level output state to the L level output state and the emitter follower circuit that transitions from the L level output state to the H level output state. When the cathode side terminal voltage Vb of each diode D increases due to the current flowing at the same time, the falling speed of the output signal Vout of the emitter follower circuit, which transitions from the H level output state to the L level output state, decreases and the two emitters simultaneously The output signal Vout of the follower circuit goes to H level, and such a decoder output may cause double selection of memory cells.

An object of the present invention is to provide an emitter follower circuit that can reduce the circuit layout area while reducing power consumption, and can output a stable binary logic signal while increasing the operating speed.

[0009]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, an input signal Vin is input to the base of an NPN transistor Tr1 whose collector is connected to the high potential power supply Vcc, and a binary logic signal in phase with the input signal Vin is output from the emitter of the NPN transistor Tr1 as an output signal Vout. At the same time, the emitter is connected to a low potential power supply VEE via a load and a current source 1, thereby forming an emitter follower circuit. The semiconductor logic circuit is a semiconductor logic circuit in which a large number of the emitter follower circuits are connected in parallel, and the load is constituted by a MOS transistor Tr2 that is always maintained in an on state with a constant gate voltage.

Further, as shown in FIG. 2, the MOS transistor is an N-channel MOS transistor whose drain is connected to the emitter of the NPN transistor Tr1, whose source is connected to the current source 1, and whose gate is connected to the high potential side power supply Vcc. It is composed of Tr2. The MOS transistor is a P-channel MOS transistor whose source is connected to the emitter of the NPN transistor Tr1, whose drain is connected to the current source 1, and whose gate is connected to the low potential power supply VEE.

Further, as shown in FIG. 2, an NPN transistor Tr3 is connected to the current source 1 for supplying current to the current source 1 to prevent saturation of the current source 1.

0012

[Operation] The emitter follower circuit to which the H level input signal Vin is input is connected to the MOS from the NPN transistor Tr1.
A constant current flows to the current source 1 through the transistor Tr3, and the emitter follower circuit to which the input signal Vin of L level is input continues a constant current through the MOS transistor Tr3 until the output signal Vout falls to the L level. Flows to source 1.

Furthermore, when the current flowing through the current source 1 decreases, a current is supplied from the NPN transistor Tr3 to prevent the current source 1 from being saturated.

[0014]

[Embodiment] A first embodiment embodying the present invention will be described below with reference to FIG. Incidentally, the same components as those of the conventional example are given the same reference numerals, and the explanation thereof will be omitted. The drain of an N-channel MOS transistor Tr2 is connected as a load to the emitter of each transistor Tr1 constituting the emitter follower circuit, the source of the transistor Tr2 is connected to the current source 1, and the gate is connected to the power supply Vcc. Therefore, the transistor Tr2 is always kept on, and its size is set to an appropriate size as a load for the transistor Tr1.

The emitter of a bipolar NPN transistor Tr3 is connected to the source of the transistor Tr2, and the collector of the transistor Tr3 is connected to the power supply Vcc, and a constant reference voltage VR is input to the base. The current source 1 receives an input signal Vin.
1 to Vinn in a transient state
A current capacity is provided to prevent the source terminal voltage Vc of r2 from rising, and the reference voltage VR of the transistor Tr3 is set so as to supply current to the current source 1 when necessary and prevent the current source 1 from being saturated. has been done.

Now, in the decoder configured as described above, for example, any one of the input signals Vin1 to Vinn is H.
When the input signal reaches the H level, a drain current flows only to the N channel MOS transistor Tr2 connected to the transistor Tr1 to which the H level input signal is input, and the other N channel MOS transistors Tr2 are cut off. That is, as shown in FIG. 3, in the N-channel MOS transistor Tr3, when a constant gate-source voltage VGS is supplied between the gate and source and the drain-source voltage VDS is changed, the drain voltage changes as shown in FIG.・If the source-to-source voltage VDS is above a certain value, the drain current ID will be almost constant, and the drain-source voltage V
When DS becomes below a certain value, the drain current ID is abruptly cut off. Therefore, the H level input signal Vin
Current flows from transistor Tr1 to transistor Tr2 in one emitter follower circuit that outputs an H-level output signal Vout based on the current, but the other emitter follower circuits are in a cut-off state, so power consumption can be reduced. Can be done. At this time, the drain current flowing through the transistor Tr2 of the emitter follower circuit that outputs the H level output signal Vout is almost constant regardless of the level of the input signal Vin input to the emitter follower circuit, so the source terminal of the transistor Tr2 By stabilizing the voltage Vc, the output voltage Vout of each emitter follower circuit can be stabilized.

If the two emitter follower circuits are simultaneously turned on when the input signal Vin is switched, the source terminal voltage Vc of each transistor Tr2 is prevented from increasing because the current capacity of the current source 1 is sufficiently secured. Thus, the output signal Vout of each emitter follower circuit can be stabilized. In the emitter follower circuit in which the output signal Vout shifts from the H level to the L level, the charge accumulated in the output terminal Tout is transferred to the output signal Vout.
Since the drain current is absorbed by the transistor Tr2 which can flow a substantially constant drain current until Vout falls to the L level, it is possible to improve the falling speed of the output signal Vout and improve the load driving ability.

On the other hand, when the emitter follower circuits except for one emitter follower circuit are cut off and the current flowing through the current source 1 decreases, the current source 1 becomes saturated and the source terminal voltage of each transistor Tr2 decreases. Vc
tends to decrease, but in this case, the transistor T
A current is supplied from r3 to the current source 1 to prevent the current source 1 from being saturated. Therefore, it is possible to prevent fluctuations in the source terminal voltage Vc of each transistor Tr2, thereby preventing unstable operation of the current source 1 due to fluctuations in the power supply Vcc, and stabilizing the output signal Vout. Furthermore, compared to the resistor R formed as a load in each emitter follower circuit in the conventional example, the N-channel MOS transistor Tr2 can be formed with a smaller layout area on the semiconductor substrate, contributing to a reduction in the circuit area of the decoder. do.

In the above embodiment, the N-channel MOS transistor Tr2 was used as the load of the emitter follower circuit, but it can also be replaced with a P-channel MOS transistor whose gate is connected to the power supply VEE.

[0020]

As described in detail above, the present invention provides an emitter follower circuit that can reduce the circuit layout area while reducing power consumption, and can output a stable logic output signal while increasing the operating speed. It can exhibit excellent effects.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram for measuring characteristics of an N-channel MOS transistor.

FIG. 4 is a characteristic diagram of an N-channel MOS transistor.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a circuit diagram showing a conventional example.

[Explanation of symbols]

Tr1 NPN transistor Tr2 MOS transistor Vcc High potential side power supply VEE Low potential side power supply Vin input signal Vout Output signal 1 Current source

Claims (4)

[Claims] Claim 1: An input signal (Vin) is input to the base of an NPN transistor (Tr1) whose collector is connected to a high potential side power supply (Vcc), and the
A binary logic signal in phase with the input signal (Vin) is output as an output signal (Vout) from the emitter of r1), and the emitter is connected to a low potential side power supply (VEE) via a load and a current source (1). a semiconductor logic circuit in which a large number of emitter follower circuits are connected in parallel, the load being a MOS transistor (Tr2) that is always kept on. logic circuit. 2. The MOS transistor is an N-channel MOS transistor whose drain is connected to the emitter of the NPN transistor (Tr1), whose source is connected to a current source (1), and whose gate is connected to a high potential power supply (Vcc). 2. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is constructed of (Tr2). 3. The MOS transistor has a source connected to the emitter of the NPN transistor (Tr1),
2. The semiconductor logic circuit according to claim 1, comprising a P-channel MOS transistor having a drain connected to a current source (1) and a gate connected to a low potential power source (VEE). 4. The current source (1) includes the current source (1).
NP that supplies current to prevent saturation of the current source (1).
2. The semiconductor logic circuit according to claim 1, further comprising an N transistor (Tr3) connected thereto.