JPH04347929A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress the through current of an output circuit consisting of complementarily connected P-type and N-type MOS transistors TRs. CONSTITUTION:A first output circuit part where P-type and N-type MOS TRs 7 and 8 are cascaded and the potential applied to an input terminal 1 appears in an output terminal 2 and a second output circuit part where P-type and N-type MOS TRs 9 and 10 are cascaded to constitute two input terminals are provided. One input terminal of the second output circuit part is connected to the input terminal of the first output circuit part, and the other input terminal is constituted as a control terminal 15, and the output terminal is connected to the output terminal of the first output circuit part. When a first potential is applied to the control terminal 15, the output terminal is set to a high impedance; and when a second potential opposite to the first potential is applied there, the potential applied to the input terminal of the first output circuit part appears in the output terminal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit composed of a P-type MOS transistor and an N-type MOS transistor connected in a complementary manner.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional output circuit of this type. An input signal S is applied to the input terminal 1, a positive power supply VDD is applied to the power supply terminal 3, and the power supply terminal 4 is connected to ground. The P-type MOS transistor 5 has a gate connected to the input terminal 1, a source connected to the power supply terminal 3, and a drain connected to the output terminal 2. The N-type MOS transistor 6 has a gate connected to the input terminal 1 , a source connected to the power supply terminal 4 , and a drain connected to the output terminal 2 , to which the output signal F is output.

FIG. 4 shows an input/output waveform diagram of this output circuit.
Shown below. In the figure, points A and D shown on the input signal S are the threshold voltages of the N-type MOS transistor 6, and the N-type MOS transistor 6 begins to conduct at point A.
At point D, the N-type MOS transistor becomes non-conductive. In addition, since points B and C correspond to the threshold voltage of the P-type MOS transistor 5, the P-type MOS transistor 5 at the point B
becomes non-conductive, and the P-type MOS transistor 5 becomes non-conductive at point C.
begins to conduct. Therefore, when the input signal S applied to the input terminal 1 changes as shown in FIG. 4, the time T1 from point A to point B while this input signal S changes from logic level L to logic level H, and During the time T2 from point C to point D during the change from logic level H to logic level L, both the P-type MOS transistor 5 and the N-type MOS transistor 6 are in a conductive state, so that the through current i flows to the power supply terminal 3- P-type MOS transistor 5
-N-type MOS transistor 6-Flows toward power supply terminal 4 as shown in FIG. In particular, in the output circuit that interfaces with an external semiconductor integrated circuit, the P-type MOS transistor 5 and the N-type MOS transistor 6 have a large channel width and a large drive capability, so the resistance when conducting is small and the through current i is large. Become.

0004

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit described above, in the process of changing the logic level of the input signal S, the through current i flowing between the power supply terminals 3 and 4 is large, so the noise on the power supply line is also large. Therefore, there is a problem in that logic malfunctions occur during electrical testing during the manufacturing process of semiconductor integrated circuit devices equipped with such output circuits. An object of the present invention is to provide an output circuit in which through-current is suppressed.

[0005]

[Means for Solving the Problems] The output circuit of the present invention has P
A first output circuit section includes a cascade-connected MOS transistor and an N-type MOS transistor, and a potential applied to the input terminal appears at the output terminal;
The second output circuit section has two input terminals configured by connecting OS transistors in series and logically connecting the gates of each transistor. One input terminal of the second output circuit section is connected to the input terminal of the first output circuit section, the other input terminal is configured as a control terminal, and the output terminal of the second output circuit section is connected to the input terminal of the first output circuit section. Connect to the output terminal,
When a first potential is applied to this control terminal, the output terminal becomes high impedance, and when a second potential opposite to this is applied, the potential applied to the input terminal of the first output circuit section is output. Configure it so that it appears on the terminal. Furthermore, the channel width of the P-type MOS transistor and N-type MOS transistor in the first output circuit section and the P-type MOS transistor and N-type MOS transistor in the second output circuit section are divided. , for example, a configuration in which it is divided into two.

[0006]

[Operation] According to the present invention, the second output circuit section is made conductive or non-conductive by the voltage applied to the control terminal, and the signal input to the input terminal is transferred to the first output circuit section whose channel width is reduced. Through-current is suppressed by outputting through.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the output circuit of the present invention. In the figure, a P-type MOS transistor 7, an N-type MOS transistor 8, and an inverter 11 constitute a first output circuit section. Moreover, P-type MOS transistor 9,
The N-type MOS transistor 10, the NAND circuit 12, the NOR circuit 13, and the inverter 14 constitute a second output circuit section. That is, in the first output circuit section, the P-type MOS transistor 7 has its gate connected to the output of the inverter 11, its source connected to the power supply terminal (VDD) 3, and its drain connected to the output terminal 2. The N-type MOS transistor 8 has a gate connected to the output of the inverter 11, a source connected to the power supply terminal (earth) 4, and a drain connected to the output terminal 2. The input of the inverter 11 is connected to the input terminal 1.

On the other hand, in the second output circuit section, a P-type MOS
The transistor 9 has a gate connected to the output of the NAND circuit 12, a source connected to the power supply terminal 3, and a drain connected to the output terminal 2. One input of the NAND circuit 12 is input terminal 1
The other input is connected to the control terminal 15, respectively. The N-type MOS transistor 10 has a gate connected to the output of the NOR circuit 13, a source connected to the power supply terminal 4, and a drain connected to the output terminal 2. One input of the NOR circuit is connected to the input terminal 1, and the other input is connected to the output of the inverter 14. An input of the inverter 14 is connected to a control terminal 15. Input terminal 1, control terminal 15
Signals S1 and S2 are applied to these terminals, respectively, and a signal F is outputted to the output terminal 2. Here, the P-type MOS transistors 7 and 9 and the N-type MOS transistors 8 and 1
0 is configured by dividing each channel width into two.

The operation of the output circuit configured as above will be explained. Here, positive logic is used, and a logically positive state, that is, logic level H, is written as "H", and a logically non-positive state, that is, logic level L, is written as "L". First, when the control signal S2 is "L", the output of the NAND circuit 12 is "
The output of the NOR circuit 13 becomes "L", and the P-type MOS transistor 9 and the N-type MOS transistor 10 become non-conductive.At this time, the output signal F receives the logic level of the input signal S1 via the inverter 11. appears.

Next, when the control signal S2 is "H", the logic of the input signal S1 is inverted by the NAND circuit 12 and the NOR circuit 13, and the logic of the input signal S1 is inverted by the P-type MOS transistor 9 and the N-type MOS transistor 9, respectively.
It is applied to the gate of the S transistor 10. Furthermore, the logic of the input signal S1 is inverted by the inverter 11 and applied to the gates of the P-type MOS transistor 7 and the N-type MOS transistor 8. At this time, if the input signal S1 is "H", the P-type MOS transistors 7 and 9 are rendered conductive and the N-type MOS transistors 8 and 10 are rendered non-conductive, so that the output signal F becomes "H". Also, input signal S1
When F is "L", P-type MOS transistors 7 and 9 become non-conductive, and N-type MOS transistors 8 and 10 become conductive, so that output signal F becomes "L".

Therefore, in this circuit, the input signal S1
The output level is the same as the input level of It becomes possible to reduce it to 1/2.

FIG. 2 is a circuit diagram showing an example of application of the present invention. Here, n output circuits shown in Fig. 1 are arranged in parallel,
Each control terminal 15 is connected to a control terminal 16 via an input circuit 17. Therefore, a signal applied to the control terminal 16 is applied via the input circuit 17 to the control terminal 15 of each of the n output circuits. Here, the control terminal 16 is connected to “
If the input of the input circuit 17 is clamped to "H" within the semiconductor integrated circuit device by the pull-up resistor 18, since the through current will decrease when "L" is applied, the control terminal 16 will be connected externally during actual use. There is no need to clamp it to "H".

Here, by increasing the ratio of the channel widths of the P-type MOS transistor 8 and the N-type MOS transistor 10 to the P-type MOS transistor 7 and the N-type MOS transistor 8, it is possible to further reduce the through current. be.

[0014]

[Effects of the Invention] As explained above, the present invention is configured such that the second output circuit section is controlled by the voltage applied to the control terminal, while the input signal is outputted by the first output circuit section. Therefore, during operation, while the total output current of each transistor in the first and second output circuit sections is obtained, the through current at that time is only in the transistors in the first output circuit section, reducing the through current. Noise on the power supply line is reduced, and stable measurements can be performed during electrical testing in the manufacturing process of semiconductor integrated circuit devices.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of an output circuit of the present invention.

FIG. 2 is a circuit diagram of an application example of the present invention.

FIG. 3 is a circuit diagram of a conventional output circuit.

FIG. 4 is a signal waveform diagram of the output circuit of FIG. 3;

FIG. 5 is a waveform diagram of a through current in the output circuit of FIG. 3;

[Explanation of symbols]

1 Input terminal 2 Output terminal 3 Power supply terminal (VDD) 4 Power terminal (ground) 7,9 P-type MOS transistor 8,10 N-type MOS transistor 11, 14 Inverter 12 NAND circuit 13 Noah circuit

Claims (2)

[Claims] [Claim 1] P-type MOS transistor and N-type MOS
A first output circuit section in which transistors are connected in cascade and a potential applied to an input terminal appears at an output terminal, a P-type MOS transistor and an N-type MOS transistor are connected in cascade, and the gates of each transistor are logically connected to each other. a second output circuit section configured with two input terminals;
One input terminal of the output circuit section is connected to the input terminal of the first output circuit section, the other input terminal is configured as a control terminal, and the output terminal is connected to the input terminal of the first output circuit section. When a first potential is applied to the control terminal, the output terminal becomes high impedance, and when a second potential opposite to this is applied, the impedance is applied to the input terminal of the first output circuit section. What is claimed is: 1. An output circuit characterized in that the output circuit is configured such that a potential applied to the output terminal appears at an output terminal. 2. The P-type MOS transistor and N-type MOS transistor of the first output circuit section and the P-type MOS transistor and N-type MOS transistor of the second output circuit section are channels of transistors constituting the output final stage. 2. The output circuit according to claim 1, wherein the output circuit is formed by dividing the width.