JPH04348679A - Framing signal generating circuit - Google Patents

Abstract

PURPOSE:To reduce a read number of times of a character ROM and to execute the processing at a high speed by providing a gate circuit capable of switching a word line between a decoder of the ROM and a memory array. CONSTITUTION:A gate circuit 6 able to switch gate wires provided between a decoder 5 of a ROM 3 storing a dot pattern of a character and a memory array 4 selects an n-th dot line of the character and selects (n+ or -1)th dot line simultaneously. Thus, the n-th dot pattern data is stored in a 1st shift register 8 and the (n+ or -1)th dot line is stored in a 2nd shift register 9. Thus, output data from the shift registers 8,9 are given to 3rd and 4th shift registers 10,11 and they are compared to obtain a framing signal in the vertical direction, then the framing in the vertical direction is implemented in a short time.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides a method for adding borders to characters (letters, symbols, pictures) when displaying them on the screen of a television receiver or the like for channel display, volume display, etc. The present invention relates to an edging signal generation circuit that causes edging.

0002

2. Description of the Related Art Display devices for displaying characters on a CRT screen are conventionally known. In this device, when displaying 24 characters x 12 lines on the screen as shown in Figure 2, for example, a RAM (for one screen) having addresses equal to the maximum displayable number (288 characters = 24 x 12) is used. and the dot pattern data of all characters to be displayed (Figure 3
) is provided with a so-called character ROM. Then, a necessary character code is written from the microcomputer to each address of the RAM. Separately, the RAM is sequentially read from the first address, and the data is applied to the character ROM, so that the dot pattern data of the required character is output from the ROM. The dot pattern data is displayed after being mixed with the video signal. In the case where a character is displayed in this manner, the output dot pattern data of the character ROM is constantly observed and bordering is performed. For example, consider a horizontal border. Three consecutive dots in the horizontal direction of the dot pattern data of FIG. 3 are extracted and shown in FIG. Now, if we consider the dot DA of the horizontal dot line Yn in FIG. 4 as a reference, there is no data in the dot DA itself (DA
When data exists in either of the 1 bits (DC and DB) before and after the dot (=0, no display) (dots are displayed when DC or DB=1), the dot DA is bordered. In addition, in the vertical direction, as shown in Fig. 5, the horizontal dot line Y
Based on the n dot DA, its upper and lower horizontal dot lines Yn
Perform a vertical comparison with ±1. In Figure 5, there is no data in the dot DA itself, and 6 of the horizontal dot line Yn±1
If there is even one data in any of the bits,
Add a border to the dots DA. By edging the dots in the horizontal and vertical directions in this way, a character with an edge as shown in FIG. 6, for example, can be obtained. FIG. 6 shows "A", and the rough hatched area shows the border.

0003

[Problem to be Solved by the Invention] However, when the vertical border is formed as shown in FIG.
It is necessary to access M three times for each dot (once to read the display character dot pattern (Yn), and twice to read the border dot pattern (Yn-1 and Yn+1)). There was a problem with the speed being slow. Also, three shift registers are required to store each dot pattern data for three readings.
There is a problem.

0004

[Means for Solving the Problems] The present invention has been made in view of the above points, and includes a decoder that decodes vertical address data of characters to be displayed, and a decoder that decodes the dot pattern data of all characters to be displayed. A memory array is arranged between the decoder and the memory array to store information corresponding to the word line and to output a logical sum of two corresponding dot pattern data when two word lines are selected at the same time. After selecting the nth or n±1st word line according to the control signal, the ROM includes a gate circuit for selecting the n±1st or nth word line, and the address of the character to be displayed. ROM
a first shift register to which dot pattern data corresponding to the nth word line of the ROM is applied; a first shift register to which dot pattern data corresponding to the nth word line of the ROM is applied; It is characterized by comprising a second shift register to which a logical OR output of dot pattern data corresponding to a line is applied, and a first comparing means for comparing output signals of the first and second shift registers.

[0005]

[Operation] According to the present invention, a gate circuit capable of switching the word line is provided between the ROM decoder that stores the dot pattern of a character and the memory array, and the nth dot line of the character is selected. Immediately after this, the n±1th dot line is selected at the same time. Therefore, the n-th dot pattern data is stored in the first shift register, and the n±1-th dot pattern data is stored in the second shift register. Therefore, a vertical edging signal can be obtained by comparing the output data of the first and second shift registers.

[0006]

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(1) is a display counter that generates various timing signals to generate a character at a desired display position in the display area on the screen, and (2) is a display counter that generates the maximum number of display characters (24 characters x 12 rows), in which a character code applied from a microcomputer (not shown) is stored.
3) All characters (64 types) displayed on the screen
dot pattern data (12 dots x 18 dots), and stores the vertical dot pattern data of each character corresponding to each word line (1152 lines = 64 types x 18 dots), and also stores two word lines. When selected at the same time, the memory array (4) outputs the logical sum of two corresponding vertical dot pattern data, and the vertical address data (18 from 0 to 17) of the character to be displayed from the display counter (1). a decoder (5) for decoding the dot position (indicating the position of the dot);
The 18-bit data (0 to 17) decoded in step 5) is applied to the 18 word lines (0 to 17) of a certain character selected in the memory array (4), and n A character ROM equipped with a gate circuit (6) that simultaneously selects the n+1st and n-1st word lines after selecting the main word line, (7) responds to the timing signal from the display counter (1). A control circuit (8) generates a control signal so that the gate circuit (6) selects a word line for character display (nth line) and a word line for bordering (n±1st line); A clock signal corresponding to a horizontal dot from the counter (1) is applied, 12-bit data corresponding to a 12-bit dot pattern is applied in parallel from the memory array (4), and a clock signal from the control circuit (7) is applied in parallel. A first shift register (9) that takes in display data in response to a control signal is supplied with a clock and data similarly to the first shift register (8), and a first shift register (9) that takes in data for edging in response to a control signal. (10) is the third shift register to which the data on the MSB side (X11 side in Figure 6) of the first shift register (8) is applied serially; (11) is the third shift register of the second shift register (9); A fourth shift register to which data from the MSB side is serially applied; (12) a first detection circuit that detects the vertical border of a character;
13) is the second method that detects the horizontal border of the character.
Detection circuit, (14) is a first OR gate that generates border signals in vertical and horizontal directions, (15) is a display output terminal that takes out a character display signal from data DA of the third shift register (10), (16) ) outputs an output signal for displaying the character itself (reference voltage V
(17) is a signal generation circuit that generates an output signal (white level relative to the video signal at reference voltage VB) and an output signal for character edging (black level relative to the video signal at reference voltage VB); This is a second OR gate that switches the switch (18) to the b side.

In FIG. 1, a code of the letter "A" as shown in FIG. 6 is stored in a predetermined address of RAM (2),
A case will be described in which bordering is performed as shown in FIG. The RAM (2) is read from the first address in response to the clock signal from the display counter (1), and the characters "
6-bit data indicating the code of "A" is stored in the memory array (
4) is applied. Note that the display at this point is the character immediately before "A". Then, the dot pattern of the character "A" is selected from the 64 types of character dot patterns. 0 to 1 shown in memory array (4)
7 is the word line of the letter "A" (Y0, Y1...Y1 in FIG.
7). On the other hand, from the display counter (1) to the decoder (5) of the ROM (3), a 5-bit address is sent to the decoder (5) of the ROM (3) to specify the vertical address of the character to be displayed at the same time as reading the start address of the RAM (2). Data is applied. The address data specifies, for example, Y0 to Y17 in FIG. 6 one by one from the top, and 18-bit word line selection data is generated in parallel from the decoder (5). The data is such that "1" is applied to the selected n-th word line and "0" is applied to the other word lines. In response to the designation of the letter "A", the control circuit (7) applies a control signal S1 to the gate circuit (6). Then, the gate circuit (6) first transmits the 18-bit decoded output of the decoder (5) as it is to the 18 word lines of the memory array. Assuming that the vertical dot position at this time is Y1 in FIG.
0,0'' dot pattern is read out by the memory array (4) and applied to the first shift register (8). At this time, the second shift register (9) is controlled by the control circuit (7) to
Do not import data. In addition, the first shift register (8) stores the dot pattern of the previous character and performs a shift operation until the data of the character "A" is applied, and the dot pattern data is displayed. The signal is applied to the third shift register (10) in accordance with the clock from the counter (1). The data is then extracted from the data DA and generated at the display output terminal (15). By generating a signal from the display output terminal (15) (dot display = "1"), the signal generation circuit (1
The switch (19) of 6) is closed, the switch (18) is switched to the b side, and the white level signal VA is transmitted. As a result, dot signals forming characters are superimposed on the video signal.

The final value of the dot pattern of the character immediately before the letter "A" is sent from the first shift register (8) to the third shift register (10), and at the same time, the final value of the dot pattern of the character immediately preceding the letter "A" is sent from the memory array (4) to the aforementioned one. A 12-bit dot pattern is loaded in parallel into the first shift register (8). Then, in response to the completion of the import, the control circuit (7)
The gate circuit (6) is switched by the control signal S2 so that the gate circuit (6) selects Y0 and Y2 in FIG. Therefore, the gate circuit (6) simultaneously selects word lines 0 and 2 of the memory array (4). At this time, the control circuit (7
) prohibits the first shift register (8) from taking in data and puts the second shift register (9) in the data taking state. Therefore, the memory array (4) outputs the logical sum of the dot data at the dot positions Y0 and Y2 in FIG.
, 0'' is generated and applied to the second shift register (9). Then, it is time to start displaying the letter “A”.
The dot pattern data of the first shift register (8) begins to be applied to the third shift register (10). at the same time,
The output of the second shift register (9) is also applied to the fourth shift register (11). Then, with all data in the third and fourth shift registers (10) and (11), data D1 is compared with data DD to DF. Data DD to DF indicate the presence or absence of both upper and lower data with respect to data DA as shown in FIG.
Vertical edging can be done just by comparing the two once. For example, when the position (X4, Y1) in FIG. 6 is data DA, "1" at the position (X5, Y2) in FIG.
” will exist in the data DF, and the first
The output of the detection circuit (12) becomes "H", the switch (20) is closed via the first OR gate (14), and the switch (18) is switched to the b side. At the same time, a "0" signal from the display output terminal (15) causes the switch (19
) opens. Therefore, the black level signal VB indicating the border
occurs on video out.

Therefore, according to the circuit of FIG. 1, it is possible to perform vertical edging in a short time.

[0010] The horizontal border is formed by the second detection circuit (13
), the third shift register (10) is used as follows. (X4, Y2) in Figure 6 is data DA
If so, the position of (X5, Y2) (data DB)
Since "1" exists in , the output of the second detection circuit (13) becomes "H". The subsequent operations are the same as in the vertical case.

Therefore, it is possible to display both vertical and horizontal borders for the dot pattern data Y2 in FIG.

[0012] In the above explanation, the memory array (4)
Regarding reading from the memory, the nth word line is read and then the n±1th word line is read, but the reverse is also possible. In that case, the order in which the control signals S1 and S2 are generated may be changed, and the order in which data is taken into the first and second shift registers (8) and (9) may be changed.

Next, a specific circuit example of the gate circuit (6) in FIG. 1 will be explained using FIG. 7. In FIG. 7, the control signal S
In mode 1, signals (0, 1, 0) are applied to terminals Yn+1, Yn, and Yn-1. Further, in the mode of the control signal S2, a signal (1, 0, 1) is applied to the terminal. By doing so, when the bit "1" of the decoder (5) is selected, the word line "1" of the memory array (4) is selected.
and word lines "0 and 2" can be selected by switching.

[0014]

[Effects of the Invention] As described above, according to the present invention, when displaying the border of a character, the character ROM
This method has the advantage of increasing processing speed because the number of times the data is read can be reduced compared to the conventional method. Furthermore, by reducing the number of reads, a shift register or the like for storing them becomes unnecessary, and the number of elements can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an edge signal generation circuit of the present invention.

FIG. 2 is a diagram showing character display on a CRT screen.

FIG. 3 is a diagram showing a dot pattern of each character.

FIG. 4 is a diagram for explaining a horizontal edging operation.

FIG. 5 is a diagram for explaining a vertical edging operation.

FIG. 6 is a diagram showing an example of a framed character.

7 is a specific circuit diagram of the gate circuit (6) in FIG. 1. FIG.

[Explanation of symbols]

(1) Display counter (2) RAM (3) ROM (4) Memory array (5) Decoder (6) Gate circuit (7) Control circuit (8) First shift register (9) Second shift register (12) First detection circuit (13) Second detection circuit

Claims (2)

[Claims] 1. A border signal generation circuit for displaying a bordered character on the screen of a display device, comprising: a decoder for decoding vertical address data of a character to be displayed; and dot patterns of all characters to be displayed. a memory array that stores data corresponding to each word line and outputs the logical sum of two corresponding dot pattern data when two word lines are selected at the same time; and the decoder and the memory array. a ROM which is arranged between the gate circuits and which selects the nth or n±1st word line and then selects the n±1st or nth word line according to a control signal; applying an address to the memory array of the ROM to specify a desired character;
a first shift register to which dot pattern data corresponding to the n-th word line of the OM is applied;
a second shift register to which a logical OR output of dot pattern data corresponding to the ±1st word line is applied; and a first comparing means for comparing output signals of the first and second shift registers. , An edging signal generating circuit characterized in that a vertical edging signal of a character is obtained from an output terminal of the first comparing means. 2. A second comparing means for comparing values before and after the output signal of the first shift register, wherein the second comparing means compares values before and after the output signal of the first shift register.
2. The edging signal generating circuit according to claim 1, wherein the edging signal in the horizontal direction of the character is obtained from the output terminal of the comparing means.