JPH0434970A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce both of the dispersion in the resistance value of a resistance element and the parasitic capacity added to the resistance element by covering the surface of the resistance element with a thicker insulating film through the intermediary of an oxidation resistant film. CONSTITUTION:A conductor film 10 is composed on the surface of a resistance element R through the intermediary of an insulating film 6 in an EEPROM having the resistance element R formed of a polycrystal silicon film 5 and then the conductor film 10 is connected to the resistance element R. In such a composition, the surface of the resistance element R is covered with the conductor film 10. Besides, the conductor film 10 is composed in the similar figure to the plane pattern of the resistance element R in the extending direction of the resistance element R while the conductor film 10 is connected to the resistance element R at one end of a signal input terminal Vin side. In such a composition, the parasitic capacity added to the resistance element R can further be reduced. Furthermore, the resistance element R comprises the resistance element of CR integrated circuit in the programming time control circuit of the EEPROM. Through these procedures, both of the written data in a memory cell M and the dispersion in the erasing thereof can be reduced thereby enabling the reliability on the EEPROM workability to be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a resistive element, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with a nonvolatile memory circuit. It is.

[Conventional technology]

The EEPROM currently being developed by the present inventor is equipped with a program time control circuit that controls the information writing time and the information erasing time. This program time control circuit has a CR integration circuit that sets (adjusts) the program time to a predetermined time.

The CR integration circuit has a basic structure of a resistance element and a capacitance element. The resistance element is formed of a polycrystalline silicon film. A resistance element formed of a polycrystalline silicon film can have smaller variations in resistance value than a resistance element formed of a semiconductor region (diffusion layer). Furthermore, the area occupied by the resistive element can be smaller than that of a resistive element formed of an aluminum film. On the other hand, the capacitive element is composed of an MO8 capacitor. This CR
Each of the resistance elements and capacitance elements that make up the integration circuit is an EEP
It has the feature that it can be formed using the manufacturing process of ROM memory cells.

The EEPROM being developed by the present inventor has an MNO8 structure MOSFET (memory element) and a select MO8FET.
A memory cell is configured. MOSFE made of MNOSg
The gate electrode of T and the gate electrode of MO5FET for selection are each formed in separate manufacturing processes. In other words, this E
EPROM is constructed with a two-layer gate structure using two layers of polycrystalline silicon films.

The resistance element of the CR integration circuit is formed from a first layer of polycrystalline silicon film in the manufacturing process.

The resistance element formed of this first layer of polycrystalline silicon film is covered with a second layer of polycrystalline silicon film with a silicon oxide film interposed therebetween. The silicon oxide film is formed by oxidizing the surface of the first polycrystalline silicon film after forming the first polycrystalline silicon film and before forming the second polycrystalline silicon film. In addition, it is formed with a relatively thin film thickness. This silicon oxide film is formed for the purpose of electrically isolating the resistive element and the second layer polycrystalline silicon film. The second layer of polycrystalline silicon film prevents the surface of the first layer of polycrystalline silicon film, which is a resistance element, from being oxidized more than necessary in the thermal oxidation process after forming the silicon oxide film. It is used as an oxidation-resistant film. That is, this oxidation-resistant film is formed for the purpose of suppressing a reduction in the cross-sectional area of the resistance element due to the thermal oxidation process and reducing variations in the resistance value of the resistance element. When this second-layer polycrystalline silicon film as an oxidation-resistant film is in a floating state, the parasitic capacitance value added to the resistance element constantly changes due to the charged charges.
Since the CR time constant varies, it is applied to a fixed potential. The parasitic capacitance is constructed by using a resistive element as one electrode, a silicon oxide film as a dielectric film, and an oxidation-resistant film as the other electrode.

Further, the fixed potential applied to the oxidation-resistant film is, for example, 5[
v].

[Problem to be solved by the invention]

However, the inventor discovered the following problems during the development of the above-mentioned EEPROM.

The resistance element of the CR integration circuit of the program time control circuit mounted on the EEFROM has a parasitic capacitance formed between it and the oxidation-resistant film, even though a fixed potential is applied to the oxidation-resistant film that covers it. is added. Specifically, the resistive element has a fixed potential applied to the oxidation-resistant film when a rising signal (for example, 5 [V]) or a falling signal (for example, 5 [V]) is input. A potential difference is generated between them, and a parasitic capacitance having an amount of charge based on this potential difference is added. The addition of this parasitic capacitance causes variations in the CR time constant of the CR integration circuit, thereby varying the programming time. For this reason, the amount of carriers (information) injected during information writing and erasing operations of memory cells varies, causing variations in the threshold voltage of MOSFETs with a 1MNO3 structure, which reduces the operational reliability of EEPROM. Sexuality decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide, in a semiconductor integrated circuit device having a resistor element, a technique capable of reducing variations in the resistance value of the resistor element and reducing parasitic capacitance added to the resistor element. It is in.

Another object of the present invention is to provide a technique capable of achieving the above object and improving the operational reliability of a semiconductor integrated circuit device having a nonvolatile memory circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device having a resistive element formed of a silicon film, a conductive film is formed on the surface of the resistive element with a silicon oxide film interposed therebetween, and each of the resistive element and the conductive film is electrically connected. Connect to.

(2) The conductor film of the means (1) is configured to have a substantially similar shape to the planar pattern of the resistor element along the extending direction of the resistor element, and the conductor film is arranged at one end of the resistor element on the signal input side. electrically connected to the element.

(3) In a semiconductor integrated circuit device having a resistor element formed of a silicon film, the surface of the resistor element is covered with an insulating film thicker than the oxidation-resistant film with an oxidation-resistant film interposed therebetween.

(4) Each of the semiconductor integrated circuit devices of the means (1) to (3) is equipped with an EtpRoM or EPROM program time control circuit, and the resistance element constitutes a resistance element of a CR integration circuit of the program time control circuit. do.

[For production]

According to the above-mentioned means (1), the surface of the resistor element is coated with the conductive film and oxidation of the surface of the resistor element can be prevented during the manufacturing process of a semiconductor integrated circuit device, so that variations in the cross-sectional area of the resistor element can be prevented. In addition, it is possible to reduce variations in the resistance value of the resistance element, and to make the resistance element and the conductive film the same potential, the resistance element is used as one electrode, the silicon oxide film is used as the dielectric film, and the conductor film is used as the other electrode. Since the parasitic capacitance used as the electrode can be made invisible, the parasitic capacitance added to the resistive element can be substantially eliminated.

According to the above-mentioned means (2), a voltage that changes over time from one end of the resistance element where a signal is inputted to the other end where a signal is outputted, and a voltage that changes over time from one end of the resistance element where a signal is input to the other end where a signal is outputted, and a voltage that is opposite to one end of the resistance element of the conductor film. Since the difference between the voltage that changes over time from one end of the resistance element to the other end facing the resistance element can be reduced, the parasitic capacitance added to the resistance element can be further reduced.

According to the above-mentioned means (3), the surface of the resistance element is coated with the oxidation-resistant film, and oxidation of the surface of the resistance element can be prevented during the manufacturing process of a semiconductor integrated circuit device, so that the cross-sectional area of the resistance element can be reduced. In addition to reducing fluctuations in the resistance value of the resistor element, the resistor element is covered with a thick insulating film to ensure a separation distance between the resistor element and other conductor films. Therefore, the parasitic capacitance added to the resistance element can be reduced.

According to the above-mentioned means (4), the EEPR○M or E
Since fluctuations in PROM programming time can be reduced, fluctuations in writing information to memory cells and fluctuations in erasing information can be reduced, and operational reliability of the EEPROM or EPROM can be improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device equipped with an EEPROM.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) The configuration of an EEPROM which is Example ① of the present invention is shown in Figure 1 (
A cross-sectional view of main parts) and a cross-sectional view taken along the line ■--■ in FIG. 1 are shown in FIG.

As shown in FIG. 1, the EEPROM is composed of a π-type semiconductor substrate 1 made of single crystal silicon. At least a p-type well region 2 is provided on the main surface of this n-type semiconductor substrate l. The p-type well region 2 or the 1-type semiconductor substrate 1
An element isolation insulating film (field insulating film) 3 is provided on the main surface of the non-active region. The element isolation insulating film 3 is formed of, for example, a silicon oxide film formed by a well-known selective oxidation method.

Memory cell M of EEPROM is MISF with MNO8 structure.
ET (memory element) Qm and select MI SF E
It is configured by series connection with T Q s. Memory cell M is arranged between data line D L (16) and source line (16).

The MISFET Qm of the MNO8 structure of the memory cell M is formed on the main surface of the f-type well region 2 in the active region within the region defined by the element isolation insulating film 3 . M
The NO8 structure MISFET Qm is mainly composed of a gate insulating film formed of a tunnel silicon oxide film 8 and a silicon nitride film 9, a gate electrode 10, a drain region, and a source region. The gate electrode 10 is formed of a gate material such as a polycrystalline silicon film. The EEPROM of this embodiment has a two-layer gate structure, and the polycrystalline silicon film is formed in the step of forming the second layer of gate material in the EEPROM manufacturing process. formed by A sidewall spacer 12 is formed on the sidewall of the gate electrode 10 . This side wall spacer 1
2 is formed of, for example, a silicon oxide film. The drain region is composed of an n-type semiconductor region 7 with a low impurity concentration. The source region is composed of an n-type semiconductor region 11 with a low impurity concentration, an n-type semiconductor region 11 with a low impurity concentration, and a Go-type semiconductor region 13 with a high impurity concentration.

M I S F E T Q for selecting memory cell M
s is formed on the main surface of the p-type well region 2 in the active region within a region defined around the element isolation insulating film 3. The selection MISFET Qs is mainly composed of a gate insulating film 4, a gate electrode 5, a drain region, and a source region. The gate insulating film 4 is formed of, for example, a silicon oxide film. The gate electrode 5 is formed of a gate material such as a polycrystalline silicon film. This polycrystalline silicon film is formed in the first layer gate material forming step in the manufacturing process. A sidewall spacer 12 is provided on the sidewall of one end of the gate electrode 5 on the drain region side. Gate electrode 5
An insulating film 6 is provided on the side wall of the other end on the source region side.
This insulating film 6 electrically isolates the gate electrode 5 and the gate electrode 10 from each other. The insulating film 6 is formed in substantially the same manufacturing process (thermal oxidation process) as the process of forming the tunnel silicon oxide film 8 of the MISFET Qm with the MNO8 structure and the process of forming the other silicon oxide film under the gate electrode 10. and is formed of a silicon oxide film. The drain region is n
It is composed of a semiconductor region 11 and a semiconductor region 13. The source region is composed of an n-type semiconductor region.

MISFETQm of MNO8 structure of the memory cell M,
Each of the selection M I S F E T Q s is substantially L D D (Lightly aped
ain) structure.

A data line 16 is connected to the go-type semiconductor region 13 which is the drain region of the select MISFET Qs of the memory cell M. The data line 16 extends on the five-layer insulating film 14,
It is connected to the go-type semiconductor region 13 through a connection hole 15 formed in this interlayer insulating film 14. EEFRO of this example
M has a one-layer wiring structure.

The data line 16 is formed of, for example, an aluminum alloy film. The aluminum alloy film is Si or Cu, or Si and C
This is an aluminum film doped with u.

Si can improve alloy spike breakdown voltage. Cu can improve electromigration breakdown voltage.

A source line 16 is connected to a go-type semiconductor region 13 formed at one end of the MISFET Qm having an MNO8 structure. The source line 16 and the data line 16 are formed of the same conductive layer. This source line 16 is applied with a power supply voltage Vcc, for example, 5 CVE during reading, and is applied with, for example, O[VV] during programming.
] is applied.

Although the chip layout of the EEFROM is not shown in the drawings, a program time control circuit that controls the information write time and the information erase time is mounted on the EEFROM. Setting of the program time of this program time control circuit is performed by a CR integration circuit, and the configuration of this CR integration circuit is shown in FIG. 4 (equivalent circuit diagram). As shown in FIG. 4, the CR integration circuit CR is arranged between the front-stage logic gate circuit L1 and the rear-stage logic gate circuit L2. The CR integration circuit CR can set each of the rise time and fall time of the output pulse signal of the front-stage logic gate circuit L1 to predetermined times.

The CR integration circuit CR is composed of a resistance element R and a capacitance element C. Vin is the input signal terminal of the CR integration circuit CR, V
out is an output signal terminal of the CR integration circuit CR.

As shown in FIGS. 1, 2, and 3 (plan views of main parts), the resistance element R is composed of a first layer polycrystalline silicon film 5. This resistance element (R) 5 extends on the element isolation insulating film 3, and is set to a predetermined resistance value, for example, about 60 [KΩ]. As shown in FIG. 3, the resistive element 5 is formed of an elongated planar pattern to increase the resistance value, and is formed of a meandering planar pattern to reduce the occupied area.

One end of the resistive element 5 on the input signal terminal Vin side is connected to the preceding stage logic gate circuit L1 via a wiring 16.

The other end of the resistive element 5 on the output signal terminal Vout side is similarly connected to the subsequent logic gate circuit L2 via the wiring 16.

The resistive element 5 is covered with a conductive film 10 with an insulating film 6 interposed therebetween, as shown in FIGS. 1 to 3.

This conductive film 10 is formed of a second layer polycrystalline silicon film, and covers substantially all of the upper and side surfaces of the resistive element 5. The conductive film 10 basically prevents the surface of the resistive element (polycrystalline silicon film) 5 from being oxidized more than necessary in the thermal oxidation step during the manufacturing process after its formation (the insulating film 6
The purpose is to avoid increasing the film thickness of the film. This conductor film 10 has a similar shape that is slightly larger than the elongated planar pattern of the resistor element 5 arranged in the lower layer (the size that covers the resistor element 5 and has a size that is equal to or larger than the size that covers the resistor element 5 and has an allowance for alignment in the manufacturing process). configured. In other words, the conductor film 10
is along the long and thin planar pattern of the resistive element 5,
It is composed of a meandering planar pattern.

One end side of the conductive film 10 facing one end of the resistive element 5 (
The input signal terminal Vin side) is electrically connected (short-circuited) to -am of the resistor element 5. Each connection of the conductor film 10 is, but is not limited to, the wiring 16
It will be held in The voltage applied to the conductive film 10 configured in this manner rises in accordance with the rising edge of the pulse signal input to the resistive element 5, and falls in accordance with the falling edge of the pulse signal input to the resistive element 5. Moreover, the voltage that changes over time from one end side to the other end of the conductor film 10 corresponds to the voltage that changes over time from the input signal terminal Vin side to the output signal terminal V out side of the resistive element 5. However, there is virtually no voltage difference between the two, that is, the amount of charge of the parasitic capacitance with the resistive element 5 as one electrode, the insulating film 6 as the dielectric film, and the conductive film 10 as the other electrode is substantially reduced. The parasitic capacitance added to the resistor element 5 can be eliminated (made invisible) by setting O to the resistor element 5.

Although the capacitive element C of the CR integrating circuit CR is not shown,
It is composed of a MIS capacitor formed in substantially the same manufacturing process as the select MISFET QS shown in FIG.

In this way, in an EEPROM having a resistance element R formed of a polycrystalline silicon film 5, a conductor film (polycrystalline silicon film) 10 is placed on the surface of the resistance element R with an insulating film (silicon oxide film) 6 interposed therebetween. and electrically connects each of the resistive elements R1 conductive films 10. With this configuration, the conductor film 1
Since the surface of the resistor element R can be coated with zero and the surface of the resistor element R can be prevented from being oxidized during the EEFROM manufacturing process, variations in the cross-sectional area of the resistor element R can be reduced and variations in the resistance value of the resistor element R can be prevented. At the same time, the resistance element R1 and the conductive film 10 are set to the same potential, so that the parasitic capacitance caused by using the resistance element R as one electrode, the insulating film 6 as a dielectric film, and the conductive film 10 as the other electrode can be hidden. Therefore, the parasitic capacitance added to the resistance element R can be substantially eliminated.

Further, the conductive film 10 is configured to have a shape substantially similar to the planar pattern of the resistive element R along the extending direction of the resistive element R, and the conductive film 10 has a shape that is substantially similar to the planar pattern of the resistive element R, and the conductive film 10 has the resistor at one end on the side of the signal input terminal Vin. It is electrically connected to element R. With this configuration, a voltage that changes over time from one end of the resistor R to which a signal is input to the other end to which a signal is output, and a voltage that changes over time from one end of the conductor film 11 opposite to one end of the resistor R Since the difference between the voltage that changes over time toward the other end of the resistance element R and the opposite end thereof can be reduced, the parasitic capacitance added to the resistance element R can be further reduced.

Further, the resistance element R constitutes a resistance element of a CR integration circuit CR of a program time control circuit of an EEPROM.

With this configuration, it is possible to reduce the variation in the programming time of the EEPR○M, so that the variation in writing information to the memory cell M and the variation in erasing information (MIS with an MNO8 structure) can be reduced.
FETQm(7) Threshold voltage variation) is reduced,
The operational reliability of EEPROM can be improved.

(Embodiment 2) Embodiment 2 is a second embodiment of the present invention in which the planar pattern of the conductive film covering the resistive element of the CR integration circuit of the program time control circuit of the EEPROM is changed.

FIG. 5 (a plan view of the main part) shows a resistance element of a CR integrating circuit of an EEPROM program time control circuit according to the embodiment (2) of the present invention.

The resistance element (R) 5 of the CR integration circuit CR in this embodiment is as follows:
As shown in FIG. 5, the meandering, closely opposing portions are integrated, and substantially all areas of the resistance element 5 are covered with a conductor film 10 formed thereon. In addition to the effect of the above-mentioned embodiment (2), the conductor film 10 configured in this manner can eliminate the separation region of the meandering and opposing regions, so that the lower resistive element 5
By reducing the meandering pitch (indicated by P in FIG. 5), the area occupied by the resistive element 5 can be reduced.

(Embodiment 2) Embodiment 2 is a third embodiment of the present invention in which the material of the film covering the resistive element of the CR integration circuit of the program time control circuit of the EEPROM is changed.

Resistance element (
R) 5 is covered with an oxidation-resistant film, such as a silicon nitride film, instead of the conductor film 10 described above, although it is not shown.

As shown in FIG. 1 of Example I, the resistance element 5 is coated with the oxidation-resistant film and then further covered with an interlayer insulating film 14 that is thicker than the oxidation-resistant film. In other words, the resistance element 5
In this case, it is possible to increase the distance between the wiring 16 and the wiring 16 that is closest to each other via the thick interlayer insulating film 14.

In this way, in an EEPROM having a resistive element R formed of a polycrystalline silicon film 5, an oxidation-resistant film is interposed on the surface of the resistive element R, and an interlayer insulating film thicker than the oxidation-resistant film is formed on the surface of the resistive element R. 14.

With this configuration, the surface of the resistance element R can be covered with the oxidation-resistant film and oxidation of the surface of the resistance element R can be prevented during the manufacturing process of the EEPROM, so that fluctuations in the cross-sectional area of the resistance element R can be reduced. In addition, variations in the resistance value of the resistance element R can be reduced, and the resistance element R is covered with a thick interlayer insulating film 14, and the separation distance between the resistance element R and other wiring 16 is reduced. Therefore, the parasitic capacitance added to the resistance element R can be reduced.

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the present invention, the resistance element of the CR integration circuit may be formed of a single crystal silicon film or an amorphous silicon film.

Further, the present invention may be applied to a CR integration circuit of a program time control circuit mounted on an EPROM, or a resistance element mounted on a semiconductor integrated circuit device.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows: In a semiconductor integrated circuit device having a resistance element, variation in the resistance value of the resistance element is reduced. At the same time, the parasitic capacitance added to this resistance element can be reduced.

Furthermore, operational reliability can be improved in a semiconductor integrated circuit device having a nonvolatile memory circuit.

[Brief explanation of the drawing]

1 is a cross-sectional view of a main part showing the structure of an EEPROM which is Embodiment I of the present invention; FIG. 2 is a cross-sectional view taken along the ff-U cutting line of the resistance element shown in FIG. 1; The figure shows a plan view of the main part of the resistor element, FIG. 4 is an equivalent circuit diagram of a CR integrating circuit incorporating the resistor element, and FIG. FIG. 3 is a plan view of a main part showing a resistance element of the CR integration circuit of FIG. In the figure, 5, 10... polycrystalline silicon film, 6... insulating film,
14...Interlayer insulating film, 15...Connection hole, 16...
Wiring, R...resistive element, C...capacitive element.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a resistive element formed of a silicon film, a conductive film is formed on the surface of the resistive element with a silicon oxide film interposed therebetween, and the resistive element and the conductive film are A semiconductor integrated circuit device characterized in that each of the above is electrically connected. 2. The conductive film has a shape substantially similar to the planar pattern of the resistive element along the extending direction of the resistive element, and the conductive film is electrically connected to the resistive element at one end on the signal input side. The semiconductor integrated circuit device according to claim 1, characterized in that: 3. In a semiconductor integrated circuit device having a resistance element formed of a silicon film, the surface of the resistance element is coated with an insulating film thicker than the oxidation resistant film with an oxidation resistant film interposed therebetween. Features of semiconductor integrated circuit devices. 4. The semiconductor integrated circuit device is EEPROM or EPR.
4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is equipped with an OM program time control circuit, and the resistor element constitutes a resistor element of a CR integration circuit of the program time control circuit. .