JPH04350940A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04350940A
JPH04350940A JP3123959A JP12395991A JPH04350940A JP H04350940 A JPH04350940 A JP H04350940A JP 3123959 A JP3123959 A JP 3123959A JP 12395991 A JP12395991 A JP 12395991A JP H04350940 A JPH04350940 A JP H04350940A
Authority
JP
Japan
Prior art keywords
layer
insulating film
bonding pad
semiconductor substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3123959A
Other languages
Japanese (ja)
Inventor
Mitsunori Yoshikawa
吉川 光憲
Toshiyuki Nakajima
中島 利行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3123959A priority Critical patent/JPH04350940A/en
Publication of JPH04350940A publication Critical patent/JPH04350940A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, which can use a desired metal for a barrier metal layer and offer high through-put. CONSTITUTION:A semiconductor substrate 1 is provided with bonding pads 3 covered with an insulating film 2. A conductive layer 4, for use in a later electrodeposition, is formed on the substrate, and an insulating film 5 is formed. A photoresist having holes above the bonding pads is applied, and it is used as an etching mask to remove the insulating film in the areas corresponding to the holes. Then, a barrier metal layer 27 is formed by a lift-off technique. When solder is applied by electrodeposition, the bonding pads are selectively plated since the other areas are covered with the insulating film. The solder plating 8 is used as a mask to selectively etch the insulating film 5 and the conductive layer 4. Finally, protruding electrodes are formed by a reflow of the solder 8. According to this method, a desired metal can be used for the barrier metal, and throughput is also improved.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置の製造技術
に関し、特に突起電極(バンプ)を有する半導体装置に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing semiconductor devices, and more particularly to a semiconductor device having protruding electrodes (bumps).

【0002】0002

【従来の技術】図6〜図13は、例えば刊行誌(三洋技
報  Vol.20  No.1  Feb.1988
  P108−115)に示されている従来の突起電極
を有する半導体装置の製造方法を工程順に示す断面図で
ある。
[Prior Art] Figures 6 to 13 are illustrated in, for example, a published magazine (Sanyo Giho Vol. 20 No. 1 Feb. 1988).
FIGS. 108-115) are cross-sectional views illustrating the conventional method for manufacturing a semiconductor device having protruding electrodes in order of steps.

【0003】ここではパンベーション膜の開口工程以降
について示す。Alバッド10と開口されたパンベーシ
ョン膜を有する基板(図示せず)(図6参照)において
、バリアメタル12を形成し(図7)と、次いでホトレ
ジスト13を用いてメッキ用マスクパターンを形成し(
図8)、その後電極用のCuメッキ14(図9)とハン
ダメッキ15(図10)を行い、マスクパターン剥離(
図11)と、バリアメタル除去(図12)を行う。最後
に“ハンダを加熱溶融し球状部16”とするリフローを
行って(図13)ハンダバンプ工程が終了される。なお
、ここで出てくるバリアメタル層やCuメッキ層は、勿
論ハンダのバリア層である。このような半導体装置の製
造方法が一般的に主流であった。
[0003] Here, the steps after the step of opening the panvation film will be described. On a substrate (not shown) having an Al pad 10 and an open panvation film (see FIG. 6), a barrier metal 12 is formed (FIG. 7), and then a plating mask pattern is formed using a photoresist 13. (
(Fig. 8), then Cu plating 14 (Fig. 9) and solder plating 15 (Fig. 10) for electrodes are performed, and the mask pattern is removed (
11) and barrier metal removal (FIG. 12). Finally, reflow is performed to heat and melt the solder to form a spherical part 16 (FIG. 13), and the solder bump process is completed. Note that the barrier metal layer and Cu plating layer that appear here are, of course, solder barrier layers. Such semiconductor device manufacturing methods have generally been mainstream.

【0004】0004

【発明が解決しようとする課題】しかし、このような方
法では前記バリア層が上述したようなCu等の選択エッ
チングが可能な金属または電界メッキが可能な金属なら
よいが、例えばPtのような選択エッチングが困難で、
かつ電界メッキも容易でない金属の場合、上述したよう
な製造方法では製造できないという問題があった。
However, in such a method, the barrier layer may be a metal that can be selectively etched such as Cu or a metal that can be electrolytically plated. Difficult to etch
In addition, in the case of metals that cannot be easily electroplated, there is a problem in that they cannot be manufactured using the above-mentioned manufacturing method.

【0005】[0005]

【課題を解決するための手段】本発明の半導体基板の製
造方法は、(a)半導体基板のボンディングパッド上に
突起電極を形成する際、前記半導体基板上に導電性のあ
る第1の層を被着形成し、続いて絶縁性の第2の層を被
着形成し、(b)前記半導体基板上に適当なホトレジス
ト等をコーティングし、ホトリソ等でボンディングパッ
ド部分を窓開けしたレジストパターンを形成し、このレ
ジストパターンをマスクとして、前記第2の層をエッチ
ングした後、適当な金属等を被着し、続いて前記レジス
トパターンを剥離除去(リフトオフ)して、ボンディン
グパッド上に第3の層を形成し、(c)前記基板に、適
当な金属等を電界メッキして、前記第3の層上にメッキ
層を形成し、このメッキ層をリフローして第4の層を形
成することからなるものである。
Means for Solving the Problems The method for manufacturing a semiconductor substrate of the present invention includes (a) forming a conductive first layer on the semiconductor substrate when forming a protruding electrode on a bonding pad of the semiconductor substrate; (b) coating the semiconductor substrate with an appropriate photoresist or the like, and forming a resist pattern in which the bonding pad portion is opened using photolithography or the like; After etching the second layer using this resist pattern as a mask, a suitable metal or the like is deposited, and then the resist pattern is peeled off (lifted off) to form a third layer on the bonding pad. (c) electrolytically plating a suitable metal or the like on the substrate to form a plating layer on the third layer, and reflowing this plating layer to form a fourth layer. It is what it is.

【0006】[0006]

【作用】この製造方法を用いることにより、バリア層に
選択エッチングが不可能な金属を用いても上述したよう
な(バンプを有する)半導体基板の製造が可能になる上
、ホトリソ工程も1回で済むためスループットが向上す
る。
[Operation] By using this manufacturing method, it is possible to manufacture a semiconductor substrate as described above (with bumps) even if a metal that cannot be selectively etched is used for the barrier layer, and the photolithography process can also be performed in one step. This improves throughput.

【0007】[0007]

【実施例】以下に、本発明を図面に示す実施例に基づい
て詳細に説明する。図1〜図5は、本発明を説明するた
めの構成断面図である。まず図1に示すように、ポリイ
ミドのような絶縁膜2で覆われたボンディングパッド3
を有する半導体基板1に、後の電界メッキ工程で用いる
導電層4を例えばTiを真空蒸着等で被着して0.3μ
mの厚さに形成し、続いてSiNX膜のような絶縁膜5
をP−CVD等で0.2μmの厚さに形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below based on embodiments shown in the drawings. 1 to 5 are configuration cross-sectional views for explaining the present invention. First, as shown in FIG. 1, a bonding pad 3 covered with an insulating film 2 such as polyimide is used.
A conductive layer 4 to be used in a later electroplating process is coated with, for example, Ti by vacuum evaporation to a semiconductor substrate 1 having a thickness of 0.3 μm.
m thickness, and then an insulating film 5 such as a SiNX film is formed.
is formed to a thickness of 0.2 μm by P-CVD or the like.

【0008】続いて図2に示すようにこの半導体基板1
にホトレジスト6をスピンコータした後、ホトリソでボ
ンディングパッド上を窓開けした後、ホトレジスト6を
マスクとして、窓開けした部分の絶縁膜5をエッチング
除去し、続いてバリアメタルになり得るTi\Pt\A
uの3層金属層7を全面に被着する。
Next, as shown in FIG.
After spin-coating a photoresist 6 on the bonding pad, a window is opened on the bonding pad using photolithography, and the insulating film 5 in the window-opened area is removed by etching using the photoresist 6 as a mask.
A three-layer metal layer 7 of u is deposited on the entire surface.

【0009】続いて図3に示すように、ホトレジスト6
を剥離除去(リフトオフ)して、バリアメタル層27を
形成し、続いてハンダを電界メッキする。このときボン
ディングパッド上以外は絶縁膜5で覆われているため、
ボンディングパッド上だけが選択的にメッキされ、メッ
キ層8を得る。
Next, as shown in FIG. 3, photoresist 6
is removed (lifted off) to form a barrier metal layer 27, and then solder is electrolytically plated. At this time, since the area other than the bonding pad is covered with the insulating film 5,
Only the bonding pads are selectively plated to obtain a plated layer 8.

【0010】続いて図4に示すように、ハンダメッキ層
8をマスクとして、絶縁膜5をHFで、続いて導電層(
Ti)をEDTA等で、順次エッチングするる
Next, as shown in FIG. 4, using the solder plating layer 8 as a mask, the insulating film 5 is coated with HF, and then the conductive layer (
Ti) is sequentially etched with EDTA etc.

【001
1】最後にハンダメッキ層8をリフローして、図5に示
すような突起電極28を得る。
001
1] Finally, the solder plating layer 8 is reflowed to obtain a protruding electrode 28 as shown in FIG.

【0012】0012

【発明の効果】本発明により、選択エッチングが不可能
な金属や電界メッキが不可能な金属をバリアメタルに使
っても、図1に示す実施例におけるようにバンプを形成
できる上、その製造方法が簡単容易であるため、スルー
プットの高いバンプ製造方法を提供することができる。
[Effects of the Invention] According to the present invention, even if a metal that cannot be selectively etched or a metal that cannot be electrolytically plated is used as a barrier metal, a bump can be formed as in the embodiment shown in FIG. 1, and a manufacturing method thereof can be used. Since this is simple and easy, it is possible to provide a bump manufacturing method with high throughput.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における製造工程の第一ステ
ップを説明するための図である。
FIG. 1 is a diagram for explaining the first step of a manufacturing process in an embodiment of the present invention.

【図2】上記実施例における製造工程の第二ステップを
示す構成説明図である。
FIG. 2 is a configuration explanatory diagram showing the second step of the manufacturing process in the above embodiment.

【図3】上記実施例における製造工程の第三ステップを
示す構成説明図である。
FIG. 3 is a configuration explanatory diagram showing the third step of the manufacturing process in the above embodiment.

【図4】上記実施例における製造工程の第四ステップを
示す構成説明図である。
FIG. 4 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the above embodiment.

【図5】上記実施例における製造工程の第五ステップを
示す構成説明図である。
FIG. 5 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the above embodiment.

【図6】従来例における製造工程の第一ステップを示す
構成説明図である。
FIG. 6 is a configuration explanatory diagram showing the first step of a manufacturing process in a conventional example.

【図7】従来例における製造工程の第二ステップを示す
構成説明図である。
FIG. 7 is a configuration explanatory diagram showing the second step of the manufacturing process in the conventional example.

【図8】従来例における製造工程の第三ステップを示す
構成説明図である。
FIG. 8 is a configuration explanatory diagram showing the third step of the manufacturing process in the conventional example.

【図9】従来例における製造工程の第四ステップを示す
構成説明図である。
FIG. 9 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the conventional example.

【図10】従来例における製造工程の第五ステップを示
す構成説明図である。
FIG. 10 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the conventional example.

【図11】従来例における製造工程の第六ステップを示
す構成説明図である。
FIG. 11 is a configuration explanatory diagram showing the sixth step of the manufacturing process in the conventional example.

【図12】従来例における製造工程の第七ステップを示
す構成説明図である。
FIG. 12 is a configuration explanatory diagram showing the seventh step of the manufacturing process in the conventional example.

【図13】従来例における製造工程の第八ステップを示
す構成説明図である。
FIG. 13 is a configuration explanatory diagram showing the eighth step of the manufacturing process in the conventional example.

【符号の説明】[Explanation of symbols]

1    半導体基板 2    絶縁膜としてのポリイミド 3    ボンディングパッド 4    導電層としてのTi 5    絶縁膜としてのSiNX膜、6    ホト
レジスト 7,27    バリアメタル層 8,28    ハンダメッキ層 10    Alバッド 11    パシベーション膜 12    バリアメタル 13    ホトレジスト層 14    Cuメッキ層 15    ハンダ
1 Semiconductor substrate 2 Polyimide as an insulating film 3 Bonding pad 4 Ti as a conductive layer 5 SiNX film as an insulating film, 6 Photoresist 7, 27 Barrier metal layer 8, 28 Solder plating layer 10 Al pad 11 Passivation film 12 Barrier metal 13 Photoresist layer 14 Cu plating layer 15 Solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  (a) 半導体基板のボンディングパ
ッド上に突起電極を形成する際、前記ボンディングパッ
ドを含む半導体基板上に導電性のある第1の層を被着形
成し、続いて絶縁性の第2の層を被着形成する工程、(
b) 前記半導体基板上に適当なホトレジスト等をコー
ティングし、ホトリソ等でボンディングパッド部分を窓
開けしたレジストパターンを形成し、このレジストパタ
ーンをマスクとして、前記第2の層をエッチングした後
、適当な金属等を被着し、続いて前記レジストパターン
を剥離除去(リフトオフ)して、ボンディングパッド上
に第3の層を形成する工程、(c) 前記基板に、適当
な金属等を電界メッキして、前記第3の層上にメッキ層
を形成し、このメッキ層をリフローして突起電極を形成
する工程からなることを特徴とした、半導体装置の製造
方法。
(a) When forming a protruding electrode on a bonding pad of a semiconductor substrate, a conductive first layer is deposited on the semiconductor substrate including the bonding pad, and then an insulating layer is formed on the semiconductor substrate including the bonding pad. Depositing a second layer (
b) Coat a suitable photoresist or the like on the semiconductor substrate, form a resist pattern with a window opened in the bonding pad portion by photolithography, etc., use this resist pattern as a mask to etch the second layer, and then etch a suitable photoresist. a step of depositing a metal etc. and then peeling off (lift-off) the resist pattern to form a third layer on the bonding pad; (c) electroplating a suitable metal etc. on the substrate; . A method of manufacturing a semiconductor device, comprising the steps of forming a plating layer on the third layer and reflowing the plating layer to form a protruding electrode.
JP3123959A 1991-05-28 1991-05-28 Manufacture of semiconductor device Pending JPH04350940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3123959A JPH04350940A (en) 1991-05-28 1991-05-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3123959A JPH04350940A (en) 1991-05-28 1991-05-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04350940A true JPH04350940A (en) 1992-12-04

Family

ID=14873577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3123959A Pending JPH04350940A (en) 1991-05-28 1991-05-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04350940A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11174056B2 (en) 2012-10-25 2021-11-16 Lantech.Com, Llc Load wrapping apparatus with controlled interventions
US11208225B2 (en) 2018-08-06 2021-12-28 Lantech.Com, Llc Stretch wrapping machine with curve fit control of dispense rate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11174056B2 (en) 2012-10-25 2021-11-16 Lantech.Com, Llc Load wrapping apparatus with controlled interventions
US11208225B2 (en) 2018-08-06 2021-12-28 Lantech.Com, Llc Stretch wrapping machine with curve fit control of dispense rate

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