JPH04357882A - Manufacture of semiconductor pressure sensor - Google Patents

Abstract

PURPOSE:To obtain a device having excellent diaphragm thickness controllability by forming a diaphragm before a diffused layer is formed. CONSTITUTION:A nitride film 7, an oxide film 6 on a P-type silicon substrate 1 of a piezo resistance forming region are removed, the substrate 1 is etched to a P<+> type buried layer 4, and a diaphragm 8 is formed. Then, after the films 7, 6 are sequentially removed, an oxide film 9 is formed, and polycrystalline silicon 10 is deposited until a groove of the diaphragm 8 is filled in. Thereafter, the silicon 10 is etched until the substrate 1 is exposed, an oxide film 11, a nitride film 12 are formed, and the film 12 on the film 9 is removed. Then, the film 9 on the upper part of an N-type epitaxial layer 5 of the periphery of an N<+> type buried layer 3 is opened, B (boron) is diffused through the opening to form a P<+> type isolation layer 13. Thus, formation of the diaphragm is conducted before the isolation layer is formed, thereby forming the diaphragm 8 before concentration of the layer 13 is reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a semiconductor pressure sensor,
In particular, it relates to a method for manufacturing a pressure sensor that utilizes the piezoresistance effect of silicon semiconductors.

0002

[Prior Art] Silicon pressure sensors are small and lightweight, have high performance, and have excellent responsiveness.
It is becoming widely used in the FA field, etc.

[0003] This type of pressure sensor is described in the Journal of the Institute of Electrical Engineers of Japan,
109C [12] (1989) P. 820 and P.820. 8
58-860, a configuration in which pressure is detected by using resistance changes due to pressure of a piezoresistive element formed on a silicon diaphragm is common, and since silicon is used as a substrate, LSI etc. Integration with integrated technology is also gaining momentum.

[0004] A cross-sectional process flow of a conventional pressure sensor of this type is shown in FIGS. 3 and 4, and will be explained in the order of FIGS.

FIG. 3(a) Sb (antimony) is diffused into a bipolar element formation region of a P-type silicon substrate 101 by a diffusion technique to form an N+ buried layer 102. As shown in FIG.

FIG. 3(b) Next, B (boron) is diffused into the piezoresistance formation region using a diffusion technique to form a P+ buried layer 103.

FIG. 3(c) Next, an N-type epitaxial layer 104 doped with P (phosphorus) is formed by epitaxial technology.
form. Next, using a diffusion technique, B is diffused into the N type epitaxial layer 104 around the N+ buried layer 102 to form a P+ isolation layer 105 that reaches from the surface of the N type epitaxial layer 104 to the P type silicon substrate.

FIG. 3(d) Next, B is diffused into the bipolar element formation region using a diffusion technique to form the base layer 106 of the NPN transistor. Then, using diffusion technology,
B is diffused into the piezoresistance formation region to form the piezoresistance 107.

FIG. 4(e) Next, P is diffused into the bipolar element formation region using a diffusion technique to form the emitter layer 108.
, to form a collector layer 109.

In the steps up to this point, the formation of the diffusion layer includes the formation of an oxide film, the removal of the oxide film from the selective diffusion region, and the re-formation of the oxide film on the selective diffusion region during diffusion. An oxide film 110 is formed on the back surface. Next, a nitride film 115 is formed on the front and back surfaces, the nitride film 115 on the front surface is removed, and a passivation film 113 is formed to protect the contact hole 111, the Al wiring 112, and the element.

FIG. 4(f) Next, a P-type silicon substrate 101
The back surface of the diaphragm 114 is etched using an alkaline etchant (KOH or the like) in alignment with the position of the piezoresistor 107. At this time, in order to accurately control the thickness of the diaphragm 114, a P+ buried layer 103 is formed. By setting the concentration of this P+ buried layer 103 to approximately 1019/cm3 or more,
It takes advantage of impurity concentration dependence, which stops etching.

0012

However, the method described above has the following problems because the diaphragm is formed after the element formation is completed.

Since the P+ isolation layer, piezoresistor, and bipolar element are formed by diffusion technology after the P+ buried layer is formed, the P+ buried layer itself is also diffused and has a low concentration. Therefore, when etching the diaphragm, 1019/c
It has the disadvantage that it is difficult to maintain a concentration of m3 or more, and it does not function satisfactorily as an etching stopper. For example, in FIG. 3(b), a P+ buried layer is formed with a concentration of 1×1020/cm3, and in FIG. 3(c), an N-type epitaxial layer is formed with a thickness of 20 μm. , in the diffusion of P+ separation layer, 1200
Heat treatment at about ℃25H is required, and as a result, P+
The concentration of the buried layer is approximately 5×10 18 /cm 3 , which is not a concentration sufficient to function as an etching stopper. For this reason, if the P+ buried layer is formed with an increased concentration of about 2 x 1020/cm3, the P+ buried layer will be diffused during the heat treatment during the formation of the P+ separation layer, and the concentration will be reduced to about 1 x 1019/cm3. N of becoming
It reaches the surface of the mold epitaxial layer, making it impossible to form piezoresistors.

[0014] In order to eliminate the above-mentioned problem of poor etching stoppage properties during diaphragm formation due to a decrease in the concentration of the P+ buried layer, the diaphragm is etched before the concentration of the P+ buried layer decreases. The purpose of the present invention is to provide a device that performs etching and has excellent controllability of diaphragm thickness.

[0015]

[Means for Solving the Problems] For the above-mentioned purpose, the present invention provides a semiconductor pressure sensor in which a diaphragm is formed before the formation of a P+ separation layer, the diaphragm portion is filled with polycrystalline silicon, and then diffused and wired. , and finally the polycrystalline silicon is removed.

[0016]

[Function] As described above, in the present invention, the diaphragm is formed before the formation of the P+ separation layer, so the concentration of the P+ buried layer does not decrease, and the layer becomes a stopper during alkali etching. It functions satisfactorily as

[0017]

Embodiment FIGS. 1 and 2 are cross-sectional process flows showing an embodiment of the present invention, and the explanation will be given below in the order of FIGS. 1A to 2H.

FIG. 1(a) Specific resistance 20Ω・cm Thickness 400
A P-type silicon substrate 1 with a thickness of about .mu.m is oxidized by a known oxidation technique to form an oxide film 2 of about 3000 .ANG. Next, a hole is formed in the oxide film 2 in the bipolar element formation region by a known photolithography etching (hereinafter abbreviated as photo-etching) technique, and through the hole, Sb (antimony) is injected into P-type silicon by a known diffusion technique. N+ diffused into the substrate 1, ρs=20Ω/□, xj=5μm
A buried layer 3 is formed. At this time, the top of the N+ buried layer 3 is reoxidized during diffusion to form an oxide film 2. (This reoxidation is the same in the subsequent diffusion, and the explanation will be omitted in the following diffusion.) Next, by using a known photo-etching technique, holes are formed in the oxide film 2 in the piezoresistance formation area, and the openings are B (boron) is converted to P by a known diffusion technique through
The P+ buried layer 4 is diffused into the type silicon substrate 1 and has a thickness of xj = 2 μm and a surface concentration of approximately 1×10 19 /cm 3 .

FIG. 1(b) Next, the oxide film 2 is removed by a known etching technique, and a film with a thickness of 20 μm and a resistivity of 2 Ω is formed at a temperature of about 1000° C. by a known epitaxial technique.
An N-type epitaxial layer 5 having a thickness of about 1.0 cm is formed. Next, an oxide film 6 of about 500 Å is formed using a known oxidation technique.
Oxidation is performed at 1000° C. for about 20 minutes to form on the front and back surfaces. Next, a nitride film 7 of about 2000 Å is formed on the front and back surfaces at a temperature of about 700° C. using a known CVD technique.

FIG. 1(c) Next, the nitride film 7 and oxide film 6 on the P-type silicon substrate 1 in the piezoresistance forming region are removed by a known photo-etching technique. Next, an alkaline etchant (KO) is applied using a known etching technique.
The P-type silicon substrate 1 is etched to the P+ buried layer 4 using a diaphragm 8. During this etching, the concentration of the P+ buried layer 4 is 2×1
019/cm3, the etching stops at the P+ buried layer 4.

FIG. 1(d) Next, the nitride film 7 and the oxide film 6 are sequentially removed by a known etching technique. Then,
Oxidation is performed in water vapor at 1000° C. for about 40 minutes using a known oxidation technique to form an oxide film 9 of about 3000 Å. Next, polycrystalline silicon 10 is deposited using a known CVD technique until the grooves of diaphragm 8 are filled.

FIG. 1(e) Next, using a known polishing technique, the polycrystalline silicon 1 is polished until the P-type silicon substrate 1 is exposed.
Subtract 0. Next, oxidation is performed at 1000° C. for about 20 minutes in an oxygen atmosphere using a known oxidation technique to form an oxide film 11 with a thickness of about 500 Å. Next, a nitride film 12 of about 2000 Å is formed using a known CVD technique, and the nitride film 12 on the oxide film 9 is removed using a known etching technique. Next, by a known photo-etching technique, N+
Oxide film 9 on top of N-type epitaxial layer 5 around buried layer 3
A hole is opened, and B (boron) is diffused into the N-type epitaxial layer 5 through the hole by a known diffusion technique.
A P+ separation layer 13 is formed.

FIG. 2(f) Next, a hole is formed in the oxide film 9 in the bipolar element formation region by a known photo-etching technique, and B(
A base layer 14, which will become the base of the NPN transistor, is formed by diffusing boron (boron). Next, a hole is formed in the oxide film 9 in the piezoresistance formation region by a known photo-etching technique, and B (boron) is diffused through the hole by a known diffusion technique to form a piezoresistor 15.

FIG. 2(g) Next, P (phosphorus) is diffused into the bipolar element formation region using known photo-etching and diffusion techniques to form the emitter layer 16 and collector layer 1.
form 7. Next, a contact hole 18 is formed using a known photo-etching technique, and then an Al wiring 19 is formed using a known vapor deposition technique and a photo-etching technique. Next, a passivation film 20 for protecting the element is formed using known CVD technology and photo-etching technology.

FIG. 2(h) Next, the nitride film 12, oxide film 11, and polycrystalline silicon 10 are etched using known etching techniques.
, the oxide film 9 of the diaphragm 8 is removed.

As described above, a semiconductor pressure sensor is manufactured by a method in which a diaphragm is formed before the step of forming a P+ separation layer.

[0027]

Effects of the Invention As described above in detail, according to the manufacturing method of the present invention, the diaphragm is formed before the P+ separation layer forming step, which requires a large amount of heat treatment, so that the P+
The diaphragm can be formed before the concentration of the buried layer is reduced. Therefore, there is an advantage that the P+ buried layer functions as a stopper for alkaline etching, allowing highly accurate etching.

[Brief explanation of drawings]

[Fig. 1] Process cross-sectional diagram of an embodiment of the present invention (Part 1)

[Figure 2
] Process cross-sectional diagram of the embodiment of the present invention (Part 2)

[Figure 3] Process sectional view of conventional example (Part 1)

[Figure 4] Process cross-sectional diagram of conventional example (Part 2)

[Explanation of symbols]

1 P-type silicon substrate 2, 6, 9, 11 Oxide film 3 N+ Embedded layer 4 P+ Embedded layer 5 N-type epitaxial layer 7,12 Nitride film 8 Diaphragm 10 Polycrystalline silicon 13 P+ Separation layer 14 Base layer 15 Piezo resistance

Claims (2)

[Claims] Claim 1: As a process for manufacturing a semiconductor pressure sensor, before forming a diffusion layer that requires a large amount of heat treatment,
A method for manufacturing a semiconductor pressure sensor, characterized in that a diaphragm is formed. 2. The method according to claim 1, wherein the diffusion layer formation requiring a large amount of heat treatment is a step of forming a separation layer between a bipolar element forming region and a piezoresistance forming region. A method for manufacturing a semiconductor pressure sensor.