JPH0435815Y2 - - Google Patents

Description

[Detailed description of the invention] (Field of industrial application) The present invention is designed to reduce the electrical overstress caused by electrostatic discharge to large-scale integrated circuits, integrated circuits, semiconductor elements, microstructured electronic components, and various electronic devices. or electromagnetic interference or the various electronic circuits mentioned above,
This invention relates to an electrostatic discharge simulator that artificially generates electrostatic discharge in order to test and evaluate the sensitivity of parts, equipment, etc. to electrostatic discharge.

(Prior Art) The electrostatic discharges to the various electronic circuits, parts, equipment, etc. mentioned above are most often caused by electrostatic charges from charged objects made of conductors insulated from the earth, especially the human body. Therefore, many conventional electrostatic discharge simulators use equivalent models of a charged human body.

Figure 3 is a diagram showing the main parts of an example of a conventional electrostatic discharge simulator, where S _DC3 is a DC power supply for charging;
SW _S is a power switch consisting of a relay switch, etc.
SW _D is a switch for opening/closing control of power switch SW _S ,
S _D is the power supply for driving the power switch SW _S , R _C is the charging resistor, C _CD is the charging/discharging capacitor, R _D is the discharging resistor,
SED is the discharge electrode, GAP is the discharge gap, and EUT is the test object.

The charging voltage of the human body normally reaches from several kV to 10-odd kV, and in some cases can reach up to 30-odd kV. Therefore, in the conventional electrostatic discharge simulator mentioned above, the output voltage of the charging DC power supply S _DC3 is ~
It is configured to be variable over a range of 30-odd kV, so that the charging voltage of the charging/discharging capacitor C _CD can be set to various required values.

In addition, the capacitance of the charge/discharge capacitor C _CD and the resistance value of the discharge resistor R _D are made equivalent to the capacitance and resistance of a charged human body, but the actual values of the capacitance and resistance of the human body vary over a fairly wide range. As typical values, the equivalent capacitance of the charging/discharging capacitor C _CD is 50 pF to 250 pF, and the equivalent resistance of the discharging resistor R _D is 100 Ω to 250 pF.
An appropriate fixed value is selected from each range of 1500Ω.

In the above-mentioned conventional electrostatic discharge simulator, after charging the charge/discharge capacitor C _CD to the required voltage, when the discharge electrode SED is gradually brought closer to the EUT under test, the product of the length of the discharge gap GAP and the atmospheric pressure increases. When the charging voltage of the discharge capacitor C _CD reaches a value corresponding to the charging voltage of the discharge capacitor C _CD , a spark discharge occurs between the discharge electrode SED and the EUT under test.
electric charge is instantaneously applied to the EUT under test.

(Problems to be solved by the invention) In the conventional electrostatic discharge simulator mentioned above, not only is the operation of gradually bringing the discharge electrode SED closer to the EUT under test, but also the discharge electrode
The approaching speed of the SED and the surface of the EUT under test,
The length of the discharge gap GAP differs for each discharge test depending on the condition of the surface directly facing the discharge electrode SED, and therefore, there is a drawback that the reproducibility of the discharge test is poor.

Discharge gap between discharge electrode SED and EUT under test
When the electrostatic discharge simulator is fixed in order to keep the GAP constant, it becomes impossible to limit the number of discharge tests to a required number of times, such as once or several times. In other words, when opening/closing the power switch SW _S , it is unavoidable that there is a time delay between opening/closing the switching control switch SW _D and opening/closing the power switch SW _S , so the switching is performed at the same time as the required number of discharge tests are completed. Even if the control switch SW _D is opened, the power switch will not turn off.
During the time delay until SW _S is opened, the charge/discharge capacitor C _CD is charged and discharged more than necessary.

To accurately perform the required number of discharge tests, move the discharge electrode SED away from the EUT under test to charge the charge/discharge capacitor C _CD , then gradually bring the discharge electrode SED closer to the EUT under test to discharge. and
The purpose can be achieved by increasing the discharge gap GAP again and charging the charging/discharging capacitor C _CD the required number of times, but not only is the operation extremely complicated, but it is also difficult to reproduce the discharge test as mentioned above. They cannot escape the flaws of being poor in their sexuality.

That is, with conventional electrostatic discharge simulators, it is impossible to accurately conduct discharge tests the required number of times with good reproducibility.

In addition, the power switch SW _S is inserted into the high voltage circuit as shown in Figure 3, but it is extremely difficult to realize a switch that is fully satisfactory as a high voltage opening/closing switch, and it is inevitable that the cost will be high. .

(Means for Solving Problems, Embodiments) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, ED ₁
and ED ₂ are counter electrodes, each peripheral portion of which is formed into a plate shape, and each central portion of which is formed with a concave portion (a protruding portion when viewed from the outside). RSP is a ring-shaped dielectric plate with holes formed in the parts corresponding to the recesses of electrodes ED ₁ and ED ₂ , and is interposed between electrodes ED ₁ and ED ₂ to be integrated with electrodes ED ₁ and ED ₂ . It has been formed. SED ₁ and SED ₂ are discharge electrodes, and are attached to respective recesses of electrodes ED ₁ and ED ₂ , respectively.
CTT is a contact with a sharp tip and a rear end attached to the periphery of electrode ED ₁ . CR is a ring-shaped magnetic core for detecting discharge current, and a contact is inserted through an insulator.
It is installed to surround the CTT. COL is magnetic core
Coil wound around CR, R _E is voltage extraction resistor, R _H
has a high resistance and is inserted between electrode ED ₁ and the ground air.
R _D is a discharging resistor, C _CD is a charging/discharging capacitor, R _C is a charging resistor, and INV is a DC/AC conversion circuit, such as an inverter circuit configured with a pair of switching elements (such as a thyristor) circuit that are alternately opened and closed. Become. S _DC1 is a current power supply, AND is a switching element, and is composed of, for example, an AND gate circuit or a switching transistor circuit. The OSC is a drive source for the DC/AC conversion circuit INV, and is composed of, for example, an AC oscillation circuit. T is a step-up transformer, CKT is a multi-stage voltage doubler rectifier circuit, and MUL is a timer, such as a multivibrator. SW _T is a changeover switch, SW _MS is a starting switch, and CED is a pulse voltage sending circuit. For example, the main components are a clock pulse oscillation circuit and a flip-flop circuit, etc., to suppress the chattering that occurs when the starting switch SW _MS is closed, and to reduce the clock pulse interval. It consists of a conventionally known appropriate circuit configured to send out one pulse voltage having a time width. A LAT is a latch circuit, for example consisting of a suitable flip-flop circuit.
WSD is a waveform shaping circuit, and S _DC2 is a DC power supply.

In addition, in the proposed electrostatic discharge simulator, a charge/discharge capacitor C _CD with an appropriate capacitance is selected from the range of 50 pF to 250 pF, and a discharge resistor is selected.
_{For R} In addition to appropriately selecting the transformer ratio of the transformer T, the multi-stage voltage doubler rectifier circuit
By appropriately configuring the CKT, the charging/discharging capacitor C _CD can be charged to a required voltage in the range of OV to several tens of kV.

After switching the changeover switch SW _T to the contact m side and bringing the tip of the contactor CTT into contact with the required location on the EUT under test, the start switch SW _MS is closed, and the pulse voltage is sent from the pulse voltage sending circuit CED. One pulse voltage is applied as a set signal to the latch circuit LAT via the changeover switch SW _T , and the AND gate circuit AND is made conductive by the output signal of the latch circuit LAT.

In response to the conduction of the AND gate circuit AND, the oscillation output of the AC oscillation circuit OSC changes to the AND gate circuit AND.
It is applied to the inverter forming the DC/AC converter circuit INV via the DC power supply S DC1, and converts the DC voltage applied from the DC power supply S _DC1 into AC voltage.

This converted AC voltage is applied to a multi-stage voltage doubler rectifier circuit CKT via a transformer T, and the output DC high voltage charges a charge/discharge capacitor C _CD via a charging resistor R _C . When the charging voltage of the charge/discharge capacitor C _CD reaches a voltage corresponding to the length of the discharge gap between the discharge electrodes SED ₁ and SED ₂ , a spark discharge occurs in the discharge gap, and the charge of the charge/discharge capacitor C _CD is instantaneously reduced. Added to EUT under test.

When a discharge electrode is added to the EUT under test, the coil is connected via the magnetic core CR provided around the contactor CTT.
The voltage drop that occurs in the voltage extraction resistor R _E due to the pulse current induced in COL causes the waveform shaping circuit WSC
After being shaped into a pulse voltage with a constant time width, it is applied as a reset signal to the latch circuit LAT, causing the output voltage of the latch circuit LAT to disappear. When the output voltage of the latch circuit LAT disappears, the AND gate circuit AND is cut off, and charging of the charge/discharge capacitor C _CD is stopped.

When the starting switch SW _MS is opened and then closed again, discharge occurs in the same manner as described above. That is,
A discharge test can be performed once each time the starting switch SW _MS is closed.

Figure 2 is a time chart to explain the above operation, where A is the open/closed state of the start switch SW _MS ;
B is the pulse voltage sent from the pulse sending circuit CED, C is the output voltage of the latch circuit LAT, D is the output voltage of the multi-stage voltage doubler rectifier circuit CKT, E is the charging voltage of the charging/discharging capacitor C _CD , F is the magnetic core CR, coil
The discharge detection voltage taken out via COL and the resistor _RE , and G are each waveform diagram of the output voltage of the waveform shaping circuit WSC.

Next, when the changeover switch SW _T is switched to contact a side to start the multivibrator MUL, its oscillation output (H in Fig. 2) is applied to the latch circuit LAT, and its output (C' in Fig. 2) When the gate circuit AND becomes conductive and a discharge test is performed in the same manner as above, the waveform shaping voltage (G' in Figure 2) of the discharge detection pulse voltage (F' in Figure 2) is applied to the latch circuit LAT. The output C' of the circuit LAT disappears, the AND gate circuit AND is cut off, and charging of the charging/discharging capacitor C _CD is stopped. The next output voltage H from the multivibrator MUL is a latch circuit.
When applied to LAT, the latch circuit LAT sends out an output again, the AND gate circuit AND conducts, and charging of the charging/discharging capacitor C _CD is resumed, as follows:
The discharge test is repeated in the same manner as above. Incidentally, FIGS. 2D' and E' are waveform diagrams of the output voltage of the multistage voltage doubler rectifier circuit CKT and the charging voltage of the charge/discharge capacitor C _CD in this case.

When the changeover switch SW _T contact is switched to the a side and the oscillation output of the multivibrator MUL is applied to the latch circuit LAT, if the oscillation period of the multivibrator MUL is longer than the time constant in the charging circuit of the charge/discharge capacitor C _CD , the discharge will start. The repetition period of is determined by the oscillation period of the multivibrator MUL.

Although FIG. 1 shows an example in which the DC/AC converter circuit INV is formed using a separately excited type circuit, it may also be formed using a self-excited type circuit.
Instead of converting the voltage of the DC power supply S _DC1 into an AC voltage by INV, for example, the commercial AC voltage can be configured to be applied to the multi-stage voltage doubler rectifier circuit CKT via a switching element, or the DC power supply S _DC1 , DC AC conversion circuit
INV, AC oscillation circuit OSC, AND gate circuit
Instead of configuring a DC high voltage source using an AND, a transformer T, and a multi-stage voltage doubler rectifier circuit CKT, for example, the output voltage of a flyback DC high voltage source can be changed to a so-called thyristor, high voltage transistor, MOS type field effect transistor, etc. It may be configured such that it is applied to the charge/discharge capacitor C _CD via a high voltage semiconductor switching element, and the opening/closing of the high voltage semiconductor switching element is controlled by the output of the latch circuit LAT.

Also, instead of detecting the discharge using the magnetic core CR, coil COL, and resistor _RE , as shown by the dotted line in Figure 1, the conductor plate CD is connected to the electrode via the dielectric plate IP.
Of course, the present invention can also be implemented by forming the electrode ED ₂ to face the electrode ED 2 so as to take out the discharge detection voltage through the capacitance between the conductor plate _CD and the electrode ED ₂ and the voltage take-out resistor R'E.

(Effect of the invention) In the electrostatic discharge simulator of the present invention, the length of the discharge gap between the discharge electrodes SED ₁ and SED ₂ can be kept constant, and the contactor CTT
Because it is configured so that a discharge test can be performed while the EUT remains in contact with the EUT under test, it is easier to handle than an electrostatic discharge simulator, which performs a discharge test by gradually bringing the discharge electrode closer to the EUT under test. In addition to being much easier, it is possible to carry out discharge while maintaining the length of the discharge gap accurately, making it possible to conduct discharge tests with good reproducibility.
A one-time discharge test can be performed by switching SW _T to the contact m side and closing the starting switch SW _MS.A discharge test can be performed by repeatedly closing the starting switch SW _MS intermittently. In addition to being able to accurately perform the desired number of operations, the changeover switch SW _T and starting switch SW _MS are inserted into the low voltage circuit, so both switches can be switched and switched without using a special high-speed switch for high voltage. It can be opened and closed quickly and there is no danger of handling it.

Although FIG. 1 shows an example in which the counter electrodes ED ₁ and ED ₂ are provided in addition to the discharge electrodes SED ₁ and SED ₂ , the present invention can be carried out even if the electrodes ED ₁ and ED ₂ are omitted. I can do it.

However, when the counter electrodes ED ₁ and ED ₂ are provided, the following effects can be produced.

That is, when the counter electrodes ED ₁ and ED ₂ are not provided, when the charge of the charging/discharging capacitor C _CD is supplied between the discharge electrodes SED ₁ and SED ₂ , the conductivity of the spark space increases at the initial stage. , in the rising process, a part of the charge of the charging/discharging capacitor C _CD is lost in the spark space, and as a result, the electric field strength in the spark space during the spark discharge generation process decreases, and this decrease in electric field strength causes the conductivity to decrease. The increasing effect of the increase in conductivity is weakened, the conductivity does not increase along the trajectory corresponding to the original rise time, and the rise time of the discharge current is compared to a constant time determined depending on the length of the discharge gap and the atmospheric pressure. As a result, the waveform of the discharge current may be distorted, which may reduce the reliability of the evaluation of the discharge test.

On the other hand, when the opposing electrodes ED ₁ and ED ₂ are provided, the capacitance formed between the opposing electrodes ED ₁ and ED ₂ when charging the charging/discharging capacitor C _CD is also charged via the high resistance R _H. Ru.

At the beginning of the spark discharge in the discharge gap between the discharge electrodes SED ₁ and SED ₂ , the charge of the charging/discharging capacitor C _CD is about to be injected into the spark space via the discharge resistor R _D , but the discharge resistor R _D and Limited by the spark resistance in the discharge gap, the amount of charge injected into the spark space is extremely small.

However, the capacitance between the counter electrodes ED ₁ and ED ₂ is connected in parallel to the discharge gap, and the capacitance between the counter electrodes ED 1 and ED ₂ is
Since the charge between ED ₂ and ED 2 is limited only by the spark resistance in the discharge gap regardless of the discharge resistance and is injected into the spark space, it is injected into the spark space from the parallel capacitance formed by the opposing electrodes ED ₁ and ED ₂ . The amount of charge that is injected from the charge/discharge capacitor C _CD is extremely large compared to the amount of charge injected from the charge/discharge capacitor C CD, and as the conductivity increases in the discharge gap, all of the charge in the parallel capacitance is injected only into the spark space. .

Therefore, if the parallel capacitance formed by the opposing electrodes ED ₁ and ED ₂ is increased appropriately and the impedance of the current path connecting this parallel capacitance and the discharge gap is made as small as possible, sparks can be prevented from the parallel capacitance. The charge is injected into the space extremely quickly, causing the discharge gap to flash over without losing much of the charge on the charge/discharge capacitor C _CD , and almost all of the charge on the charge/discharge capacitor C _CD is added to the EUT under test. At the same time, the waveform of the discharge current can be made extremely close to the ideal waveform, and the reliability of the discharge test can be improved.

In this case, the energy applied to the EUT under test is determined only by the current discharged from the charge/discharge capacitor C _CD via the discharge gap and is independent of the charge of the parallel capacitor.

Furthermore, if the value of the resistor R _H inserted between the electrode ED ₁ and the ground air is selected to be sufficiently high compared to the impedance of the EUT under test, there is no possibility that the discharge current will be shunted to the resistor R _H.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining its operation, and Fig. 3 is a diagram showing an embodiment of the present invention.
The figure shows the main parts of a conventional electrostatic discharge simulator. ED ₁ and ED ₂ ... counter electrode, RSP ring-shaped dielectric plate, SED ₁ , SED ₂ and SED ... discharge electrode, CTT ... contactor. , CR...Annular magnetic core, COL...
...Coil, R _E and R′ _E ...Resistance for voltage extraction, R _H ...
...High resistance, R _D ...Discharging resistance, C _CD ...Charging and discharging capacitor, R _C ...Charging resistance, INV ...DC AC conversion circuit, S _DC1 , S _DC2 , S _DC3 and S _D ...DC power supply,
AND...Switching circuit, OSC...Drive source, T...Transformer, CKT...Multi-stage voltage doubler rectifier circuit, MUL...
Timer, SW _T , SW _MS , SW _S and SW _D ... Switch, CED ... Pulse voltage sending circuit, LAT ... Latch circuit, WSC ... Waveform shaping circuit, GAP ... Discharge gap, EUT ... Test object , CD...conductor plate, IP
...It is a dielectric plate.

Claims (1)

[Claims for Utility Model Registration] (1) A discharge resistor and a discharge electrode for applying the electric charge of a charging/discharging capacitor to a test object, and a DC high voltage source for applying a DC voltage to the charging/discharging capacitor via the charging resistor. , selects the periodic pulse voltage sent from the timer or the pulse voltage formed and sent in response to the closing of the manual on/off switch, and applies the changeover switch to the latch circuit as a set signal, and detects the discharge current of the charge/discharge capacitor. and a circuit that applies the output of the latch circuit as an opening/closing control signal for a switching element that opens and closes the output of the DC high voltage source. Electrostatic discharge simulator. (2) The utility model registration claim 1, wherein the DC high voltage source comprises a DC power supply, a DC/AC conversion circuit to which its output voltage is applied, and a multistage voltage doubler rectifier circuit to which its converted output is applied. Electrostatic discharge simulator. (3) The electrostatic discharge simulator according to claim 1, wherein the DC high voltage source is a multi-stage voltage doubler rectifier circuit to which the output voltage of a commercial AC power source or the like is applied. (4) The electrostatic discharge simulator according to claim 1, wherein the DC high voltage source is a flyback DC high voltage source. (5) The electrostatic discharge simulator according to claim 1, wherein the discharge current detection element is an electromagnetic induction type detection element. (6) The electrostatic discharge simulator according to claim 1, wherein the discharge current detection element is an electrostatic induction type detection element.