JPH04358197A - Gradation driving circuit of liquid crystal display - Google Patents

Abstract

PURPOSE:To decrease the number of external power input lines and the number of analog switches. CONSTITUTION:(n)-Bit gradation display data and a lump type liquid crystal driving voltage are inputted to gradation driving circuits 4 and 5 for each display picture element. The gradation driving circuits 4 and 5 each have a shift register for storing gradation display data of one line, a line memory circuit for storing the gradation display data of one line stored in the shift register at the same time, a pulse-width converting circuit which converts the gradation display data in the line memory circuit into pulses having width corresponding to its gradation display level, and a circuit which samples and holds the lump type liquid crystal driving voltage according to the output of the pulse-width converting circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation drive circuit that enables halftone display in a liquid crystal display.

0002

2. Description of the Related Art Conventionally, the circuit shown in FIG. 8 is well known as a driving circuit for a liquid crystal display. In FIG. 8, a plurality of X electrode lines (X1, X2,...) and Y electrode lines (Y1, Y2,...) are configured in a matrix,
An active element 21 such as a TFT (thin film transistor) and a liquid crystal display element 22 are formed at the intersection of each X electrode line and Y electrode line.

The Y electrode line is also called a data signal line, and is connected to a display signal circuit 23 that outputs a display data signal for each liquid crystal display element 22. The X electrode line is also called a scanning signal line, and is connected to a scanning signal circuit 24 that sequentially outputs scanning signals. The active element 21 is driven by a line sequential driving method in which the X electrode line is sequentially scanned and driven, and the active element 21 on the X electrode line is turned on (active state) in synchronization with the scanning of the X electrode line. Hour display signal circuit 23
A display data signal is outputted from the active element 21 in the on state, and the data signal is written to the corresponding liquid crystal display element 22 via the active element 21 in the on state. Note that attempts have also been made to provide a storage capacitor 25 in the liquid crystal display element 22 as necessary to improve the charge retention characteristics of the liquid crystal display element 22.

[0004] Here, by making the amplitude value of the data signal voltage written to the liquid crystal display element 22 variable, the writing voltage or charge amount to the liquid crystal display element 22 is variably controlled, and the light transmittance of the liquid crystal is variably controlled. be able to. This method is called a voltage modulation driving method, and is a typical driving method for displaying halftones on a liquid crystal display. As a liquid crystal drive circuit that enables gradation display using this voltage modulation driving method, for example, "LCD driver HD66310T manufactured by Hitachi, Ltd." shown in FIG. 9 is known.

[0005] FIG. 9 shows a screen that can display eight gradations.
3-bit display data D0j, D1 corresponding to liquid crystal pixels
j, D2j are input to the first latch circuit 31 in synchronization with the clock signal CL2. The display data signal input to the first latch circuit 31 is then input to the second latch circuit 32 in synchronization with the clock signal CL1. and,
The output of the second latch circuit 32 is input to the voltage selector circuit 33.

This voltage selector circuit 33 is composed of a decoder circuit, etc., and outputs data onto one of 23 =8 output lines based on a 3-bit input signal, for example. It is something. In this circuit configuration, the output of the voltage selector circuit 33 selects one of the analog switches 34 1 to 34 8 in the next stage and turns it on, and outputs the output from the eight power input lines connected to the analog switches 34 1 to 34 8 . It operates to output any one of V0 to V7 to the driver output Yn.

The liquid crystal driver circuit manufactured by Hitachi, Ltd. includes 160 drive circuits (for 160 dots) as shown in FIG. Further, the liquid crystal display device includes a number of liquid crystal driver circuits corresponding to the number of pixels in one horizontal scanning line. The transfer from the first latch circuit 31 to the second latch circuit 32 is performed after display data for one horizontal scanning line is input to the latch circuit 31.

[0008]

However, the liquid crystal display drive circuit having the above structure has the following problems. (1) When achieving multiple gradations, external power inputs are required for the number of gradations equivalent to the number of gradations reproduced.Furthermore, when integrating the drive circuit (IC), the area occupied by the wiring system of the power input line inside the IC increases. increases and becomes uneconomical. (2) The number of analog switches constituted by P-MOS, N-MOS, FET, etc. is also required to reproduce the gradation, which is not economical when considering integration.

The present invention solves the above problems and provides a low-cost gradation drive circuit for a liquid crystal display that can perform multi-gradation display, reduce the number of external power input lines and the number of analog switches, and provide a low-cost gradation drive circuit for a liquid crystal display. The purpose is to

0010

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides two methods for driving each display pixel using a voltage modulation driving method.
In the gradation drive circuit of a liquid crystal display that performs gradation display at n levels (n is an integer of 2 or more), after storing n-bit gradation display data for one display pixel for a predetermined number of display pixels, a memory circuit for outputting, a pulse width control circuit for converting the gradation display data stored in the memory circuit into a pulse having a width corresponding to the gradation display level;
A circuit for sampling and holding the ramp-shaped liquid crystal driving voltage based on the output of the pulse width control circuit was provided.

[0011]

[Operation] According to the present invention, since the gradation drive circuit for a liquid crystal display is configured as described above, the memory circuit stores n-bit gradation display data for each pixel for a predetermined number of display pixels (for example, 1 line) and then simultaneously outputs to the pulse width control circuit. The pulse width output circuit converts the gradation display data into a pulse having a width corresponding to the gradation display level, and outputs the pulse to the sample hold circuit. Then, the sample and hold circuit samples and holds the ramp-shaped liquid crystal drive voltage based on the output of the pulse width control circuit, and generates a 2n level analog voltage.

0012

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a liquid crystal display equipped with a gray scale driving circuit according to an embodiment of the present invention. This liquid crystal display includes a liquid crystal panel 1,
Scanning circuits 2 and 3 provide scan pulses to the liquid crystal panel 1, gradation drive circuits 4 and 5 supply voltage modulation signals to the liquid crystal panel 1, and scan timing signals (start signal and scan clock) of the scan circuits 2 and 3. signal) and gradation display data (n bits/pixel) which is input data to the gradation drive circuits 4 and 5
and an LCD control section 6 that outputs a liquid crystal drive voltage to be supplied to the gradation drive circuits 4 and 5. The liquid crystal panel 1 includes a plurality of rows of scanning electrode lines G1 to GN and a plurality of data electrode lines D1 to DM extending in a direction perpendicular to the scanning electrode lines G1 to GN.
, a thin film transistor (not shown) formed to be electrically connected to the scanning electrode line and the data electrode line at the intersection thereof, and a color filter (not shown).

FIG. 2 is a block diagram showing the configuration of a gradation drive circuit according to an embodiment of the present invention, FIG. 3 is a characteristic diagram showing the relationship between voltage applied to liquid crystal and transmittance, and FIG. 4 is a diagram showing the relationship between voltage applied to a liquid crystal and transmittance. A block diagram per dot of the gradation drive circuit, FIG. 5 is an operation time chart of the gradation drive circuit according to the embodiment of the present invention, and FIG. 6 is a pulse width control circuit in the gradation drive circuit according to the embodiment of the present invention. This is a circuit diagram per dot.

First, an outline of the operation of the gradation drive circuit according to the embodiment of the present invention will be explained based on FIGS. 2, 3, and 5. The shift register circuit 7 in FIG. 2 has gradation display data (D1
~Dn) and the start signal (S) synchronized with the horizontal synchronization signal.
Storage starts at the timing of TA), and thereafter, storage is performed sequentially at the timing of shift lock (CLK). After storing the gradation display data for one horizontal scanning line (data electrode lines D1 to DM), the data is stored in the line memory circuit 8 at the timing of the load signal (LOAD). This shift register circuit 7 and line memory circuit 8 correspond to the memory circuit in the present invention.

The gradation display data for one horizontal scanning line stored in the line memory circuit 8 is simultaneously input to the pulse width control circuit 9 for all dots, and the pulse width control clock (CPG)
The pulse width is converted to an arbitrary pulse width according to the conditions of the gradation display data, and is output from the pulse width control circuit 9. The output signal of the pulse width control circuit 9 is converted to a predetermined level by the level shifter circuit 10, and then sent to the sample hold switching circuit 1.
1 is input.

The sample-and-hold switching circuit 11 is provided for each dot, and is selected according to the conditions of the sample-and-hold switching signal (CH), and samples the ramp-shaped liquid crystal drive voltage during the output period of the pulse width control circuit 9. Charge the hold circuit 12. The hold voltage after charging is determined by the timing of the output enable signal (OE) from the buffer amplifier circuit 13 via the level shifter circuit 10. ) is output. here,
The liquid crystal drive voltage is set in the range of V0 to V2 in FIG.

Note that since FIG. 2 shows one chip of the gradation drive circuit, the number of output terminals m of the buffer amplifier circuit 13 is
When is equal to the number M of dots in one horizontal scanning line in FIG. 1, one circuit in FIG. 2 is required to output the gradation drive voltage for one horizontal scanning line. However, if m is 1/10 of M, for example, 10 circuits as shown in FIG. 2 are required to output the gradation drive voltage for one horizontal scanning line. In that case, the shift register circuit 7 and the line memory circuit 8 will have a capacity for 1/10 line, and the shift register circuit 7 in the 10 gradation drive circuits will have a capacity of 1/10 line.
After the gradation display data for a total of one horizontal scanning line is stored, it is simultaneously stored in the line memory circuits 8 of the ten gradation drive circuits at the timing of the load signal. The input operation from the line memory circuit 8 to the pulse width control circuit 9 is also similar.

Next, the operation of the gradation drive circuit according to the embodiment of the present invention will be explained in detail based on FIGS. 4, 5, and 6. FIG. 4 shows the pulse width control circuit 9 to the buffer amplifier circuit 1.
3 shows the Xth one dot, and FIG. 6 shows one dot of the pulse width control circuit 9. As shown in FIGS. 5 and 6, when the n-1 line of gradation display data starts to be stored in the shift register circuit 7, the n-2 line of gradation display data already stored in the line memory circuit 8 Do
~Dn is input to the coincidence circuit 9-3 of the pulse width control circuit 9 in accordance with the rise timing of the load signal (Q1-
Qn) to be done.

The load signal is input to the set terminal (S) of the flip-flop circuit (F/F) constituting the pulse width storage circuit 9-1, and is input to the counter 9- which measures the number of pulse width control clocks. 2 reset terminal (RS
T). The clock number counter 9-2 measures the number of pulse width control clocks and provides the measurement results (q1 to qn).
is input to the matching circuit 9-3.

The coincidence circuit 9-3 operates between each output bit of the line memory circuit 8 and the clock number counter 9-2 (Q1 and q
1, ... Input the signal output from the AND result of Qn-1 and qn-1, Qn and qn) and the pulse width control clock to the reset terminal (R) of the pulse width storage circuit 9-1. . After being set by the load signal, the pulse width memory circuit 9-1 holds the state while being reset by the output signal of the coincidence circuit 9-3, and stores the output signal of the pulse width control circuit 9 (PO
X).

In this embodiment, as shown in FIG.
The gradation display data of the n-2 line is 8 bits all 0, n
The gradation display data for the −1 line and the n line is 8 bits all 1. If the 8 bits are all 0, the coincidence circuit 9-
3 generates an output signal, and 1 if 8 bits are all 1s.
Coincidence circuit 9-3 generates an output signal at the timing of the last pulse width control clock in the horizontal scanning line. And 8
The analog output voltage when all bits are 0 corresponds to V1 in FIG. 3, and the analog output voltage when all 8 bits are 1 corresponds to V2 in FIG. Note that the interval of the pulse width control clock is changed in order to perform gradation correction, but this point will be described later.

Next, the output signal (P
OX) is input to the common terminal SW-C of the changeover switch 11-1 in the sample-hold changeover circuit 11 via the level shifter circuit 10, and is input from the terminal (SWa-1 or SWa-2) selected by the changeover signal. It is output to the sample hold circuit 12. In this embodiment, the switching signal is set to a mode in which the polarity is inverted every horizontal synchronization. When the switching signal is at the "H" level, the changeover switch 11-1 selects SWa-1,
Analog switch SWa in sample hold circuit 12
-3 turns on. Further, when the switching signal is at the "L" level, the changeover switch SWa-2 is selected and the analog switch SWa-4 is turned on. Note that instead of inverting the polarity for each horizontal synchronization, it is also possible to only invert the polarity for each field, which is normally performed.

The on time of each analog switch is the pulse width time (POX) generated in the pulse width control circuit 9, and the on time of each analog switch is the pulse width time (POX) generated in the pulse width control circuit 9. The liquid crystal drive circuit is connected to the pulse width time (POX), and each hold capacitor circuit S/H-1
, charge S/H-2. The hold voltage of each capacitor circuit holds the liquid crystal drive voltage when the pulse width is off. The sample and hold circuit 12 includes two circuits: a hold capacitor circuit and output buffer circuits BF-P and BF-N.

The buffer circuit BF-P is a non-inverting buffer amplifier with a gain of 1, and the buffer circuit BF-N is a non-inverting buffer amplifier with a gain of 1.
This is an inverted buffer amplifier with a gain of 1. During the period when the hold capacitor circuit S/H-1 is selected, the buffer circuit BF-N is selected and the hold voltage of the capacitor circuit S/H-2 is inverted and output. Also, during the period when the hold capacitor S/H-2 is selected,
Buffer circuit BF-P is selected and capacitor circuit S/
The H- hold voltage is output non-inverted.

The buffer amplifier circuit 13 outputs the output voltage (OX) of the sample and hold circuit 12 during the period when the output enable signal is on, and drives the liquid crystal with alternating current. The common terminal in the sample and hold circuit 12 is set near the liquid crystal applied voltage Vo in FIG. In this embodiment, the externally input liquid crystal drive voltage waveform is a linear ramp-like drive waveform with a period of one horizontal scanning line. Furthermore, in this embodiment, the liquid crystal drive voltage is set to a drive voltage value that includes the liquid crystal bias voltage (V0 to V1 voltage);
There is no harm in inputting a liquid crystal drive voltage waveform with a DC bias of 1 voltage).

FIG. 7 is an explanatory diagram of a gradation correction method using a gradation driving circuit according to an embodiment of the present invention. This gradation correction is performed by modulating the time for charging the hold capacitor in the sample and hold circuit 12 with the external liquid crystal drive voltage by modulating the pulse width control clock interval (TCPG1, TCPG2). In other words, the interval of the pulse width control clock is widened (T
If CPG1) is set, the timing at which the matching circuit 9-3 generates the output signal will be delayed, the slope of the voltage applied to the liquid crystal will become larger, and the interval between the pulse width control clocks will be narrowed (
TCPG2) If set, the timing at which the matching circuit 9-3 generates the output signal will be earlier, and the slope of the voltage applied to the liquid crystal display will be smaller. By using this, the interval of the pulse width control clock can be set to the desired value. By setting, desired gradation correction is performed.

Furthermore, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0028]

Effects of the Invention As described above in detail, according to the present invention, gradation display data is converted into a pulse with a width corresponding to the level, and a ramp-shaped liquid crystal driving voltage is sampled based on the pulse. Since it is configured to hold, the following effects are achieved. (1) The number of external power supplies required to obtain the same number of gradations can be significantly reduced. (2) The number of analog switches required to obtain the same number of gradations can be reduced. (3) Since there is no need to drive the external power supply circuit with alternating current, the load on the power supply circuit can be reduced. (4) The pulse width control circuit is configured to compare each bit of the gradation display data with the count value of the pulse width control clock, detect a match, and output a pulse with a width corresponding to the gradation display level. By doing so, it is possible to apply any gradation correction voltage to the liquid crystal display.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a liquid crystal display equipped with a gray scale driving circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a gradation drive circuit according to an embodiment of the present invention.

FIG. 3 is a characteristic diagram showing the relationship between applied voltage to liquid crystal and transmittance.

FIG. 4 is a block diagram of a gradation drive circuit per dot according to an embodiment of the present invention.

FIG. 5 is an operation time chart of the gradation drive circuit according to the embodiment of the present invention.

FIG. 6 is a circuit diagram of a pulse width control circuit per dot in a gradation drive circuit according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram of a gradation correction method using a gradation driving circuit according to an embodiment of the present invention.

FIG. 8 is a circuit diagram showing the circuit configuration of a conventional liquid crystal display.

FIG. 9 is a block diagram showing a conventional gradation drive circuit.

[Explanation of symbols]

1 Liquid crystal panels 2, 3 Scanning circuits 4, 5 Gradation drive circuit 6 LCD control section 7 Shift register circuit 8
Line memory circuit 9 Pulse width control circuit 10 Level shifter circuit 11 Sample and hold switching circuit 12
Sample hold circuit 13 Buffer amplifier circuit

Claims (4)

[Claims] [Claim 1] Each display pixel is driven by two pixels using a voltage modulation driving method.
In a gradation drive circuit for a liquid crystal display that displays gradations at n levels (n is an integer of 2 or more), (a) 1
a memory circuit that simultaneously outputs n-bit gradation display data for a predetermined number of display pixels after storing it for a predetermined number of display pixels;
b) a pulse width control circuit that converts the gradation display data stored in the memory circuit into a pulse having a width corresponding to the gradation display level; A gradation drive circuit for a liquid crystal display, comprising: a circuit that samples and holds a liquid crystal drive voltage. [Claim 2] The pulse width control circuit compares each bit of the gradation display data with the count value of the pulse width control clock, detects a match, and outputs a pulse with a width corresponding to the gradation display level. 2. The gradation drive circuit for a liquid crystal display according to claim 1. 3. The gradation drive circuit for a liquid crystal display according to claim 1, wherein the sample and hold circuit inverts the held liquid crystal drive voltage for each horizontal scanning line of gradation display data. 4. The gradation drive circuit for a liquid crystal display according to claim 2, wherein the pulse interval of the pulse width control clock is modulated in accordance with gradation correction characteristics.