JPH04360310A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To expand the operation enable range at a low frequency area of a dynamic flip-flop circuit. CONSTITUTION:In the flip-flop circuit in which a 1st inverter gate 1 and a 1st buffer gate 2 are connected by providing transfer gates 3a, 3b, 4a, 4b to respective input terminals, a 2nd inverter gate 5 with a shall drive capability is provided in anti-parallel with the 1st inverter gate 1 and a 2nd buffer gate 6 with a small drive capability is provided in anti-parallel with the 1st buffer gate 2.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit used in various semiconductor logic integrated circuits.

0002

2. Description of the Related Art In GaAs logic integrated circuits capable of high frequency operation, dynamic operation flip-flop circuits are often used.

FIG. 8 shows an example of a divide-by-2 circuit using such a GaAs dynamic flip-flop. The input terminal of the inverter gate 21 is the transfer gate 2
The input terminal of the buffer gate 22 is connected to the output terminal of the inverter gate 21 via the transfer gate 24, thereby forming a flip-flop circuit. The output terminal of the flip-flop circuit is feedback-connected to the input terminal to form a frequency dividing circuit. The two transfer gates 23 and 24 are controlled by clocks CK and /CK having mutually opposite phases.

FIG. 9 is a timing diagram of this frequency dividing circuit. When the clock CK attains the "H" level, the "1" data at the node d is transferred to the node a via the transfer gate 23. Thereafter, node b is inverted to "0" by the data transferred to node a after a delay time Δtpd. During this time, the potentials of nodes c and d are kept constant by the charges accumulated in the capacitance of node c.

Next, when the clock /CK becomes "H" level, the data at the node b is transferred to the node c via the transfer gate 24. After the delay time Δtpd, the data transferred to the node c inverts the data at the node d. During this time, the potentials of nodes a and b are kept constant by the charges accumulated in the capacitance of node a.

In this manner, data is transferred each time the clocks CK and /CK alternately go to the "H" level and "L" level, and a frequency division operation is performed. The maximum operating frequency fmax of this frequency dividing circuit is determined by the delay time Δtpd of the inverter gate 21 and buffer gate 22, and fmax
x = 1/(2・Δtpd)

It is expressed as: This is compared to when using a normal static flip-flop, that is, when there is a two-stage gate delay in the flip-flop.
This means that 2 to 3 times faster operation can be expected.

However, in dynamic flip-flop circuits, low frequency operation is conversely limited. That is, in FIG. 8, if the input capacitance of the inverter gate 21 and the buffer gate 2 is C and the charge thereof is C·ΔV, this decreases with time due to the leakage current ΔI. When the potential becomes less than the logical threshold value Vth of the inverter gate 21 or the buffer gate 22, data cannot be held and is inverted. At this time, the lowest operating frequency is expressed as fmin=1/{2·C(ΔV−Vth)/ΔI}.

[0009]

[Problems to be Solved by the Invention] As described above, dynamic flip-flop circuits are excellent in high frequency operation, but there is a minimum operating frequency determined by the amount of accumulated charge and leakage current, and operation in a low frequency region is difficult. The problem was that it was limited. The present invention has been made in view of these points, and an object of the present invention is to provide a flip-flop circuit that operates from a low frequency range to a high frequency range. [Structure of the invention]

0010

[Means for Solving the Problems] The present invention provides an inverter
Based on a dynamic flip-flop circuit consisting of a gate and a buffer gate connected via a transfer gate, a memory function circuit with low driving capacity is added to the inverter gate and buffer gate to achieve high performance in the low frequency region. It is characterized by enabling static operation.

Specifically, first, a differential type first transistor is connected to two signal input terminals via first transfer gates each having a differential input terminal controlled by a first clock. the first clock via an inverter gate and a second transfer gate whose differential input terminals are respectively controlled by a second clock having an inverse relationship with the first clock.
The first terminal connected to the differential output terminal of the inverter gate of
In a flip-flop circuit having a buffer gate of It is characterized in that a second buffer gate having a smaller driving capacity is connected in antiparallel between the input and output terminals.

Second, a differential first inverter gate whose differential input terminals are connected to two signal input terminals via first transfer gates each controlled by a first clock; a buffer gate having a differential input terminal connected to a differential output terminal of an inverter gate via a second transfer gate each controlled by a second clock having an inverse relationship with the first clock; The buffer circuit is characterized in that memory circuits with low driving capability are connected to the input terminals of the first inverter gate and the buffer gate, respectively.

[0013]

[Operation] The flip-flop circuit according to the present invention is basically a dynamic flip-flop, and is capable of high frequency operation similar to the conventional one. In the low frequency range, the memory function added to the inverter gate and buffer gate results in static operation, and the lowest operating frequency is 0.
It is possible to operate up to

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a GaAs film according to an embodiment of the present invention.
This is a divide-by-2 circuit using a flip-flop circuit. 1st
A flip-flop circuit is constructed by connecting a differential inverter gate 1 and a first differential buffer gate 2 with transfer gates 3a, 3b, 4a, and 4b provided at their respective input terminals. has been done. The output terminal of the flip-flop circuit is feedback-connected to the input terminal to form a frequency dividing circuit.

The first differential inverter gate 1 includes:
A second differential inverter gate 5 is connected in antiparallel, and a second differential buffer gate 6 is similarly connected in antiparallel to the first buffer gate 2.

Due to the anti-parallel connection of the first inverter gate 1 and the second inverter gate 5, this part itself constitutes a static flip-flop;
It is assumed that the driving capability of the second inverter gate 5 is sufficiently smaller than that of the first inverter gate 1. Similarly, by anti-parallel connection of the first buffer gate 2 and the second buffer gate 6, this part itself constitutes a static flip-flop, but the driving capability of the second buffer gate 6 is It is assumed that it is sufficiently smaller than that of the first buffer gate 2.

FIG. 2 shows the inverter gates 1 and 5 of FIG.
, 6 and an example SCFL of buffer gate 2.
It is an inverter. Driver MES that constitutes a differential circuit
MESFET-M3, M for level shifting is connected to the output terminal of FET-M1, M2 and load resistance RL.
4 are provided. Inverter gates 1 and 5 and buffer gates 2 and 6 are simply opposite in their input/output terminal relationships. FIG. 3 is a timing diagram for explaining the operation of the frequency dividing circuit according to this embodiment. Its operation is basically the same as the conventional one.

FIG. 3 shows operation at relatively low frequencies. In other words, the clocks CK and /CK are alternately set to “1”.
, "0", and the operation is performed at such a frequency that the discharge of the signal charges accumulated in the nodes A and D becomes a problem. In this case, in a conventional dynamic circuit without the second inverter gate 5 and second buffer gate 6,
After the transfer gates 3a, 3b or 4a, 4b are turned off, the node A or C shows a potential change as shown by the broken line in the figure, and the node that should hold the data "1" state changes to "1". It becomes impossible to hold the battery, leading to malfunction.

On the other hand, in this embodiment, after the "1" level of the node A or C starts to decrease, the output terminal of the second inverter gate 5 or the second buffer gate 6 is output with a delay of Δt. becomes “1”. therefore,
These nodes A or C are recharged by the second inverter gate 5 or buffer gate 6, respectively. In other words, it operates statically in the low frequency range.

On the other hand, in the high frequency range, the second inverter
The presence of gate 5 and second buffer gate 6 can be ignored and a dynamic frequency division operation is performed. This is because the driving ability of the second inverter gate 5 and the second buffer gate 6 is small, and therefore the effect of increasing leakage at nodes A and C due to their provision is small, and also because the driving ability of the second inverter gate 5 and the second buffer gate 6 is small, The change in potential at nodes A and C, respectively
This is because the delay time Δt until the signal is fed back is large, so the original dynamic operation is not hindered.

Specifically, for example, the first inverter gate 1 and the first buffer gate 1 forming the main circuit of FIG.
For gate 2, MESFET-M1 to M in FIG.
The second inverter gate 5 and the second buffer gate 6 are constructed using MESFETs M1 to M4 having a gate width of 8 μm. Further, the transfer gates 3a, 3b, 4a, 4b in FIG. 1 have a gate width of 54
It is composed of μm MESFET.

In this case, the frequency dividing circuit of FIG.
It was confirmed that it operates stably in the 4.0 GHz range. Incidentally, in a conventional frequency divider circuit without the first inverter gate 5 and the second buffer gate 6, the operating frequency was 2 GHz to 14.3 GHz.

FIG. 4 shows a modification of the embodiment shown in FIG. In this embodiment, the output terminals of the second inverter gate 5 and the second buffer gate 6 are respectively
It is fed back to the input terminals of the first inverter gate 1 and the first buffer gate 2 via resistors R1, R2, R3, and R4 of about 3 kΩ.

According to this embodiment, the second inverter
The provision of the gate 5 and the second buffer gate 6 suppresses the increase in leakage at the input terminals of the first inverter gate 1 and the first buffer gate 2, resulting in maximum operation that is almost the same as before. You can get the frequency.

FIG. 5 shows a GaAs frequency divider circuit according to another embodiment of the present invention. In this embodiment, a non-differential inverter gate 11 and a buffer gate 12 are used, and transfer gates 13 and 14 are provided at their input terminals to form a flip-flop circuit. This embodiment also shows a case where the output terminal of a flip-flop is feedback-connected to the input terminal to form a frequency dividing circuit.

The input terminal of the inverter gate 11 has the following:
A latch circuit 15 is provided as a memory circuit in which two inverter gates 15a and 15b having sufficiently small driving capacity are connected in antiparallel. Similarly, at the input terminal of the buffer gate 12, there is a latch circuit 1 in which two inverter gates 16a and 16b with sufficiently low driving capacity are connected in antiparallel.
6 is provided.

Inverter gates 11, 15a, 15b
, 16a, 16b are, for example, an inverter circuit configured by a normally-off type MESFET-M11 and a normally-on type MESFET-M12 as shown in FIG. 6(a), and a normally-off type MESFET-M14 and a normally-on type MESFET-M13. It consists of a source follower circuit. The buffer gate 12 is a normally-on MESFET as shown in FIG. 6(b).
-M21 and a normally-off MESFET-M22.

According to this embodiment, the latch circuit 15,1
By the function of 6, data is retained in the low frequency operation region. In the high frequency range, if the driving capabilities of the latch circuits 15 and 16 are sufficiently small, the influence of increased leakage is small, and high frequency operation almost the same as in the conventional art is possible. Therefore, the same effects as in the previous embodiment can be obtained.

In fact, for the inverter gate 11 and the buffer gate 12, MESFETs with a gate width of 80 μm and the configurations shown in FIGS. 6(a) and 6(b) are used, and the latch circuit 15
, 16 inverter gates have a gate width of 8 μm.
As a result of constructing a frequency dividing circuit using ESFETs and MESFETs having a gate width of 50 μm for the transfer gates 13 and 14, stable operation was confirmed from 0 Hz to 8.0 GHz. The operating frequency range when latch circuits 15 and 16 were not provided was 2 GHz to 8.5 GHz.

In this embodiment as well, as shown in FIG.
Inverter gate 15a among latch circuits 15 and 16
, 16a, an increase in leakage at the input nodes of the inverter gate 11 and the buffer gate 12 can be suppressed. Resistance R
is, for example, about 3 kΩ. As a result, stable operation from 0 Hz to 8.3 GHz was confirmed under the same conditions as the specific example of the embodiment shown in FIG. 5 above.

The present invention is not limited to the above embodiments. For example, in the embodiment, the flip-flop was constructed as an integrated circuit of GaAs-MESFET, but other semiconductor materials may be used, and in addition to MESFET, MOS
FETs and junction FETs can also be used.

[0033]

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a flip-flop circuit that enables wideband operation by performing static operation in a low frequency range while ensuring dynamic operation in a high frequency range. Can be done.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a GaAs frequency dividing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an SCFL circuit used in the same embodiment.

FIG. 3 is an operation timing chart of the same embodiment.

FIG. 4 is a diagram showing a frequency dividing circuit of an embodiment that is a modification of FIG. 1;

FIG. 5 is a diagram showing a GaAs frequency divider circuit according to another embodiment of the present invention.

FIG. 6 is a diagram showing an inverter gate and a buffer used in the same embodiment.

FIG. 7 is a diagram showing a frequency dividing circuit of an embodiment that is a modification of FIG. 5;

FIG. 8 is a diagram showing a conventional dynamic GaAs frequency divider circuit.

FIG. 9 is an operation timing diagram of FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1...First inverter gate, 2...First buffer gate, 3a, 3b, 4a, 4b...Transfer gate, 5...Second inverter gate, 6...Second buffer gate, 11...Inverter - Gate, 12... Buffer gate, 13, 14... Transfer gate, 15, 16... Latch circuit, R1 to R4, R... Resistor.

Claims (3)

[Claims] 1. A differential first inverter gate, each of which has a differential input terminal connected to two signal input terminals via a first transfer gate controlled by a first clock; a first buffer connected to the differential output terminals of the first inverter gate via second transfer gates each having an input terminal controlled by a second clock having an inverse relationship with the first clock;・
A second inverter gate and a second inverter gate having a smaller driving capacity are connected in antiparallel between the input and output terminals of the first inverter gate and the first inverter gate.
an inverter gate, and a second buffer gate having a smaller driving capacity and connected in antiparallel between the input and output terminals of the first buffer gate. circuit. 2. The second inverter gate and the second
The output terminal of the buffer gate is connected to the input terminal of the first inverter gate and the first inverter gate through resistors, respectively.
2. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is connected to an input terminal of a buffer gate of the flip-flop circuit. 3. An inverter gate whose input terminal is connected to a signal input terminal via a first transfer gate controlled by a first clock; and an inverter gate whose input terminal is in an inverse relationship with the first clock. a buffer gate connected to the output terminal of the inverter gate via a second transfer gate controlled by a second clock;
a first memory circuit provided at the input terminal of the inverter gate and having a smaller driving capacity than the inverter gate; and a second memory circuit provided at the input terminal of the buffer gate and having a smaller driving capacity than the buffer gate. and,
A flip-flop circuit characterized by being equipped with.