JPH04364556A - Data transfer method - Google Patents

Abstract

PURPOSE:To use a prefetch buffer efficiently according to the transfer capability of an input/output device. CONSTITUTION:A channel controller 300 is provided with the prefetch data buffer 302 for multi-channel common use and receives transfer capability data on input/output devices 500-504 from a central processing unit 100 each time data are transferred. A prefetch data buffer control circuit 303 controls the use state of the prefetch data buffer 302 and secures the user areas of the prefetch data buffer for channel devices 400-404 according to the transfer performance of the input/output device received with an input/output instruction 1. A data transfer control circuit 304 performs memory access corresponding to the secured use areas of the prefetch data buffer 302 to control data transfer between a main storage device 200 and the input/output devices 500-504.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data transfer method.
In particular, the present invention relates to a data transfer method having a channel control device that transfers data from a main memory connected to a central processing unit to an input/output device.

0002

[Prior Art] In conventional data transfer methods, a channel control device is connected to a main storage device and a central processing unit, controls a plurality of channel devices, and controls input/output devices connected to each channel device. It has a prefetch data buffer that is shared by multiple channels and is used when transferring data from the storage device. Since this prefetch data buffer has a fixed storage capacity, a constant prefetch data buffer is prepared regardless of the performance of the input/output device connected under the channel.

0003

[Problems to be Solved by the Invention] In the conventional data transfer method described above, the channel control device has a fixed prefetch data buffer size for each channel device, so there are input/output devices with different transfer performance under the channel device. When a high-performance input/output device is connected, the prefetch data buffer required for transfer by a high-performance input/output device is prepared, so the prefetch data buffer connected to an input/output device with low transfer performance is wasted. was there. In recent years, input/output devices have become faster and faster, and input/output devices with high transfer performance and
Since the combination of low input/output devices is unavoidable, there is a problem in that the waste of prefetch data buffers also increases.

0004

[Means for Solving the Problems] A data transfer method of the present invention includes controlling a plurality of channel devices connected to a main storage device and a central processing unit, and controlling an input/output device connected to the main storage device and the channel device. a shared prefetch data buffer that temporarily stores data to be transferred to the plurality of channel devices; and a shared prefetch data buffer that temporarily stores data to be transferred to the plurality of channel devices; a first means for receiving the transfer performance of the prefetch data buffer; a second means for managing the usage status of the prefetch data buffer and securing a usage area of the prefetch data buffer according to the transfer performance; and third means for controlling data transfer between the main storage device and the input/output device by performing memory access according to the used area.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which channel devices 400 to 404 are provided under a channel control device 300.
The case where four are connected is shown.

In FIG. 1, a central processing unit 100 issues an input/output command 1 to a channel control device 300 when performing input/output processing on data for arithmetic processing. This input/output command 1 includes information indicating the transfer performance of the channel device that transfers data. The main storage device 200 is connected to the central processing unit 100 and the channel control device 300,
reads and writes data from input/output devices required by the central processing unit 100 via the channel device 400;
A one-word memory reply 4 is sent out for each memory request 3 issued by the channel control device 300. The channel control device 300 controls the channel device according to the input/output command 1 issued by the central processing unit 100, and transfers data between the main storage device and the input/output device. Channel devices 400, 401,...403 are input/output devices 50
0, 501, . . , 503, and transfers the transfer output data 7 received from the channel control device 300 to the input/output device 500.

[0007] The channel control circuit 301 decodes the input/output command 1 received from the central processing unit 100 and outputs the input/output command 1.
The data transfer control circuit 3 secures a prefetch data buffer area according to the transfer performance of the channel device displayed in
04 and the channel device 400 to transfer data. The prefetch data buffer 302 is a buffer that writes and reads transfer data read from the main memory device 200 prior to transfer to an address designated by the prefetch data buffer control circuit 303.

The prefetch data buffer control circuit 303 is
The write address 16 and the read address 15 are generated according to the usable area of the prefetch data buffer 302 allocated to the channel device to be transferred with reference to the prefetch data buffer management display flag 305, and the data transfer control circuit 304 is The number of memory accesses is limited to control the amount of data in the prefetch data buffer 302, and when the usage area of the prefetch data buffer 302 allocated to the channel device becomes full, a request suppression signal 13 is output, and memory requests are processed in the order in which they are made. The channel device number of the memory request is memorized, and each time the data input register 306 receives memory reply data 4, it outputs the write address 16 of the prefetch data buffer 302, and when outputting the memory reply data to the channel device, it outputs the write address 16. The read address 15 of the data buffer 302 and the channel device number 11 to be transferred are sent.

The data transfer control circuit 304 controls the main storage device 20 according to the data transfer instruction 8 of the channel control circuit 301.
0 is accessed by memory request 3, and continues to send out memory request 3 for each channel device until the request inhibit signal 13 for each channel is output from the prefetch data buffer control circuit 303, and sends out memory request 3 once. Each time, a request sending signal 14 for each channel device is transmitted to the prefetch data buffer control circuit 303.

The display flag 305 is assigned one flag per unit area of the prefetch data buffer 302, and is composed of a channel device number and a bit in use, and the corresponding unit area of the prefetch data buffer 302 is assigned to a channel control device. When the channel device connected to 300 is being used for data transfer, its channel device number and the in-use bit are set to “1”, and when it is not in use, the in-use bit is set to 0.
This flag is set and reset by the channel control circuit 301 and is always prefetched by the data buffer 302.
Displaying usage status.

Data input register 306 is a register for receiving memory reply data 4 from main storage device 200 and writing it to prefetch data buffer 302 . The data output register 307 is the prefetch data buffer 3
This is a register for sending the data 6 read from 02 to the channel device designated by the channel device number 11 output from the prefetch data buffer control circuit 303.

Next, the operation of this embodiment will be explained.
The central processing unit 100 issues the input/output command 1 to the channel control device 300, and in the channel control device 300, the channel control circuit 301 decodes the input/output command 1, confirms the transfer performance of the channel device, and sets the display flag 305. Referring to the display signal 10, it is determined whether the input/output instruction 1 can be executed based on the usage status of the prefetch data buffer 302, and if the usage area of the prefetch data buffer 302 necessary to execute the input/output instruction 1 is insufficient. If not, the central processing unit 100 is informed that execution is impossible because the prefetch buffer is busy (BUSY). When the prefetch buffer is BUSY, the central processing unit 100 selects another input/output device path and issues the input/output command 1. Channel control circuit 301
is the display flag 30 if input/output instruction 1 is executable.
Set the channel device number and in-use bit “1” to 5, and set the prefetch data buffer 3 necessary for executing input/output instruction 1.
Secure the area for use in 02. Then, the channel device designated by input/output command 1 is notified of the start of transfer via signal line 0. Channel devices 400 to 404 that received the notification
is in the state of waiting for input/output data. Furthermore, the channel control circuit 301 provides transfer control information 8 to the data transfer control circuit 304 to start memory access. The data transfer control circuit 304, which has received the transfer control information 8, starts sending the memory request 3 and sends a request sending signal 14 to the prefetch data buffer control circuit 303 every time the memory request 3 is sent. The request signal 14 continues to be sent out until the request suppression signal 13 is output from the buffer control circuit 303. The prefetch data buffer control circuit 303 references the display signal 10 of the display flag 305 and sends a request suppression signal to the data transfer control circuit 304 when the use area of the prefetch data buffer 302 assigned to the channel device 400 that is currently transferring becomes full. Outputs 13.

[0013] Also, a plurality of channel devices 400 to 404
If they are performing transfer operations at the same time, the memory request 3 of each channel device is sent out according to the used area of the prefetch data buffer 302 allocated to each channel device. When memory reply 4 arrives, data input register 306 stores memory reply data 5 in prefetch data buffer 302 at the address specified by prefetch data buffer control circuit 303 . Prefetch data buffer 3
02 outputs memory reply data 5 at the address specified by the prefetch data buffer control circuit 303 to the data output register 307 as data 6. When the data output register 307 receives the data 6, it sends the transfer data 7 to the channel device designated by the number 11 by the prefetch data buffer control circuit 303, and when the sending is completed, the data output register 307 sends the data send signal 12 to the prefetch data buffer control circuit 303. to notify completion of data output. The prefetch data buffer control circuit 303 has a data output register 307.
When data early output signal 12 comes from request suppression signal 1
3 and permits the data transfer control circuit 304 to send memory request 3. The above operation is repeated until the transfer amount specified by the input/output command 1 is completed, and when the data transfer is completed, the channel control circuit 301 controls the central processing unit 1
The end report 2 of the input/output command 1 is output to 00, and the operation of the channel control device 300 is ended.

FIG. 2 shows the prefetch data buffer 3 of this embodiment.
02 and the display flag 305, one display flag for prefetch data buffer management is associated with each unit area of the prefetch data buffer 302, and the display flag 305 corresponds to the unit area of the prefetch data buffer 302. It consists of the device number of the channel device being used and an in-use bit indicating whether or not it is in use, and when the in-use bit is "0", the corresponding prefetch data buffer 30
Indicates that unit area 2 is unused. The channel control circuit 301 determines the required number of unit areas of the prefetch data buffer 302 from the number of words of prefetch data required to execute the input/output instruction 1, and calculates the device number of the channel device to be used and the bits in use prior to the transfer operation. Set. As soon as the transfer operation is completed, the in-use bit is reset.

[0015]

As explained above, the present invention shares the prefetch data buffer of a plurality of channel devices to which input/output devices with different transfer capabilities are connected, and performs transfer operations according to the transfer capabilities of the input/output devices. By making the usage amount of the prefetch data buffer variable, the prefetch data buffer can be used efficiently. Furthermore, since input/output devices with high transfer performance and input/output devices with low transfer performance can be freely connected, there is an effect that the prefetch data buffer is not wasted.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of this embodiment.

[Explanation of symbols]

100 Central processing unit 200 Main storage device 300 Channel control device 301 Channel control circuit 302 Prefetch data buffer 303 Prefetch data buffer control circuit 304
Data transfer control circuit 305 Display flag 306 Data input register 307 Data output register

Claims (1)

[Claims] 1. A channel control device connected to a main storage device and a central processing unit, controlling a plurality of channel devices, and transferring data between the main storage device and an input/output device connected to the channel device. , a shared prefetch data buffer for temporarily storing data to be transferred to the plurality of channel devices, and first means for receiving transfer performance of the channel device or input/output device from the central processing unit for each data transfer; a second means for managing the usage status of the prefetch data buffer and securing a usage area of the prefetch data buffer according to the transfer performance; and a second means for performing memory access according to the usage area of the prefetch data buffer and the main memory. A data transfer method, comprising: third means for controlling data transfer between the device and the input/output device.