JPH04365218A - Pulse width varying circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable pulse width circuit that converts a digital signal into a pulse having a pulse width corresponding to the digital signal.

0002

2. Description of the Related Art Conventionally, in a circuit for varying the pulse width of a digital signal as shown in FIGS. The pulse width was varied by changing the resistance value of the variable resistor 13, and by performing an OR operation between the input signal and the delayed signal using the logic element 16.

A and B show voltage waveforms at respective locations.

0004

[Problems to be Solved by the Invention] However, in conventional pulse width variable circuits, the pulse width was changed by changing the resistance value of the variable resistor, so the problem was that the pulse width could not be controlled by digital signals. was there. SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that can control pulse width using a digital signal in order to solve this conventional problem.

[0005]

[Means for Solving the Problems] In order to solve the above problems, the present invention continuously connects a capacitive element, a logic element that charges and discharges the capacitive element, and a logic element that shapes the waveform of the charging and discharging waveform. The input signal includes a plurality of waveform-shaped signal transmission paths, a switch element inserted into each of the plurality of transmission paths to control transmission of the waveform-shaped signal, and a selection circuit that selectively conducts the switch element. The configuration is such that a logical operation between the output signal and the output signal of the switch element is performed by a logic element, and the pulse width can be varied.

[0006]

[Operation] In the variable pulse width circuit configured as described above, the waveform-shaped signal is treated as a delayed signal. Some delayed signals are selected from the plurality of delayed signals. The selection of the delay signal is controlled by a digital signal, and the pulse width is varied by a logical operation between the selected delay signal and the input signal, so the pulse width is controlled by the digital signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. In FIG. 1, the input terminal and output terminal of the inverter 1a are respectively connected to a signal input terminal 8, one input terminal of a multi-input OR gate 6, and a capacitor 3a and an input terminal of the inverter 2a. The output terminal of inverter 2a is connected to the input terminal of inverter 1b and switch element 4a.
The control terminal and output terminal of the switch 4a are connected to one output terminal of the selection circuit 7 and the resistor 5a and O
It is connected to one input terminal of the R gate 6.

The output terminal of the OR gate 6 is the signal output terminal 9
The input terminal of the selection circuit 7 is connected to the selection signal input terminal 10. The input/output terminals of inverters 1b to 1n, capacitors 3b to 3n, inverters 2b to 2n, and switch elements 4b to 4n are connected in the same manner. The control terminals and output terminals of the switch elements 4b to 4n are the output terminals and resistors 5b to 5n of the selection circuit 7, respectively.
and the input terminals of the OR gate 6, and the input terminals of the selection circuit are connected to the selection signal input terminals 10b to 10n.

Next, the operation of the circuit will be explained. Inverter 1
a, the inverter 2a, and the capacitor 3a constitute a delay circuit, and the inverter 2a outputs a delayed signal with respect to the input signal. Inverters 1b to 1 continuously connected in the same way
n, inverters 2b to 2n, and capacitors 3b to 3n generate n-1 delayed signals. The n delayed signals generated are transferred to the n switch elements 4a to 4n and the selection circuit 7.
One or more are selected by the selection signals 10a to 10n transmitted through the gates, and the selected delay signal and the input signal are logically summed by the OR gate 6 and output.

In FIG. 2, the switches 4a and 4b are turned on,
A timing diagram when obtaining a delayed signal is shown.

[0011]

Effects of the Invention As explained above, the present invention selects some of the plurality of delayed signals, controls the selection of the delayed signals by a digital signal, and performs an OR operation between the selected delayed signals and the input signal. Since the configuration is such that the pulse width can be varied by performing this, there is an effect that the pulse width can be controlled by a digital signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a variable pulse width circuit of the present invention.

FIG. 2 is an operational waveform diagram of the variable pulse width circuit of the present invention.

FIG. 3 is a variable pulse width circuit showing a conventional example.

FIG. 4 is an operational waveform diagram in a conventional example.

[Explanation of symbols]

1a~1n, 2a~2n Inverter 3a~3n
Capacitors 4a-4n Switch elements 5a-5n Pull-down resistor 6 (n+1) input OR gate 7 Selection circuit 8 Signal input terminal 9 Signal output terminal 10a-10n Selection signal input terminal 11a-11n Selection delay signal 12, 15 Inverter 13 Variable Resistor 14 Capacitor 16 2-input OR gate 17 Signal input terminal 18 Signal output terminal

Claims (1)

[Claims] 1. A plurality of capacitive elements, a logic element that charges and discharges the capacitive element, and a logic element that shapes the charging and discharging waveforms are continuously connected, and a transmission path for a plurality of waveform-shaped signals is provided. and a switch element that controls a signal on the transmission path, a selection circuit that selectively turns on the switch element, and a logic element that performs a logical operation on an input signal and an output signal of the switch element. A variable pulse width circuit featuring: