JPH043661B2 - - Google Patents
Info
- Publication number
- JPH043661B2 JPH043661B2 JP57113177A JP11317782A JPH043661B2 JP H043661 B2 JPH043661 B2 JP H043661B2 JP 57113177 A JP57113177 A JP 57113177A JP 11317782 A JP11317782 A JP 11317782A JP H043661 B2 JPH043661 B2 JP H043661B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- fine powder
- wafer
- substrate
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
- H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
- H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
- H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6322—Formation by thermal treatments
Landscapes
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法の改良に関す
る。特に、シリコン（Si）基板表面に付着したシ
リコン（Si）微粉末に起因する異常拡散領域の発
生を伴わない半導体装置の製造方法の改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an improvement in a method for manufacturing a semiconductor device. In particular, the present invention relates to an improvement in a method of manufacturing a semiconductor device that does not involve the occurrence of abnormal diffusion regions caused by fine silicon (Si) powder adhering to the surface of a silicon (Si) substrate.
(2) 技術の背景
シリコン（Si）よりなる半導体装置は直径３
〔インチ〕あるいは５〔インチ〕程度の薄板（以下
ウエーハという。）を単位として製造されるが、
そのハンドリング工程またはラツピング工程等に
おいて、シリコン（Si）の微粉末が発生しやす
い。もちろん、これらの微粉末を除去するための
洗浄工程が実施されてはいるが、なおかつ、ウエ
ーハ上に微粉末が残留することは避け難い。(2) Technical background Semiconductor devices made of silicon (Si) have a diameter of 3
It is manufactured in units of thin plates (hereinafter referred to as wafers) of about [inch] or 5 [inches].
During the handling process, wrapping process, etc., fine silicon (Si) powder is likely to be generated. Of course, a cleaning process is carried out to remove these fine powders, but it is still unavoidable that the fine powders remain on the wafer.
ところで、シリコン（Si）ウエーハはその製造
工程において、すでに何らかの不純物を含有して
いるため、その微粉末も当然のことながら同様に
不純物を含有している。この微粉末がウエーハに
付着した状態で素子形成工程を実行した場合、拡
散工程においてその微粉末に含有されていた不純
物が基板中に拡散する。そのため、その領域にお
ける不純物濃度が予期せざるものとなり、部分的
に耐圧の悪化を招来したり、リーク電流の増大を
原因することになる。いずれにせよ、所望の状態
と異なる状態となり、しかもそうした欠陥が発見
された場合、そのウエーハは、使用不可能となる
ため製造歩留りが低下し問題である。 By the way, since a silicon (Si) wafer already contains some impurities during its manufacturing process, its fine powder naturally also contains impurities. When an element forming process is performed with this fine powder attached to the wafer, impurities contained in the fine powder are diffused into the substrate in the diffusion process. Therefore, the impurity concentration in that region becomes unexpected, leading to a partial deterioration of breakdown voltage and an increase in leakage current. In any case, if the wafer is in a state different from the desired state and such a defect is discovered, the wafer becomes unusable, resulting in a decrease in manufacturing yield, which is a problem.
例えば、ｐ型不純物を含有するシリコン（Si）
基板を１，100〔℃〕の湿性酸素（水蒸気を含む酸
素雰囲気）中で60分酸化すると仮定して、仮に、
基板上に直径25〔μm〕程度のn+型不純物を含むシ
リコン（Si）微粉末が存在すると、その周囲に直
径６〔μm〕程度、深さ２〔μm〕程度の異常拡散層
の発生が認められる。 For example, silicon (Si) containing p-type impurities
Assuming that the substrate is oxidized for 60 minutes in humid oxygen (oxygen atmosphere containing water vapor) at 1,100 [℃], hypothetically,
If silicon (Si) fine powder containing n + type impurities with a diameter of about 25 [μm] exists on a substrate, an abnormal diffusion layer with a diameter of about 6 [μm] and a depth of about 2 [μm] will occur around it. Is recognized.
(3) 従来技術と問題点
この欠点を解消するため、従来技術において
は、(1)ウエーハスクライバを使用して機械的に除
去する、(2)界面活性剤等を使用して化学的に除去
する、(3)ポリビニルアルコール（PVA）やレジ
スト剤等の高分子化合物等の塗布、除去を繰り返
し行なつて除去する、(4)シリコン（Si）基板の酸
化、エツチングを繰り返し行なつて除去する等の
方法が使用されているが、(1)、(2)、(3)の方法はい
ずれも比較的粒径の大きな微粉に対しては効果的
であるが、径の小さいものに対してはその効果が
不十分であり、しかも、(1)では基板表面に機械的
な損傷を与えるという欠点を有し、(2)は、使用さ
れる界面活性剤等の薬剤が、続くウエーハプロセ
スにおいて使用される種々の薬剤と化学反応を起
こす可能性がある等の欠点を有する。一方、(4)の
方法は、微粉除去の効果は十分であるが、ただ、
同時に拡散が起こり異常拡散領域が発生するとい
う欠点がある。(3) Conventional technology and problems In order to solve this drawback, the conventional technology uses (1) mechanical removal using a wafer scriber, and (2) chemical removal using a surfactant or the like. (3) Removal by repeatedly applying and removing polymeric compounds such as polyvinyl alcohol (PVA) and resist agent; (4) Removal by repeatedly oxidizing and etching the silicon (Si) substrate. Methods (1), (2), and (3) are all effective for fine powder with a relatively large particle size, but they are effective for fine powder with a small particle size. In addition, (1) has the disadvantage that it causes mechanical damage to the substrate surface, and (2) has the disadvantage that the surfactants and other chemicals used are insufficient in the subsequent wafer process. It has drawbacks such as the possibility of chemical reactions with the various drugs used. On the other hand, method (4) is effective in removing fine particles, but
There is a drawback that diffusion occurs at the same time and an abnormal diffusion region occurs.
(4) 発明の目的
本発明の目的は、この欠点を解消することにあ
り、シリコン（Si）基板表面に付着したシリコン
（Si）微粉末に起因する異常拡散領域の発生を伴
わず、結果として、リーク電流の増加等が有効に
防止され、製造歩留りが良好な半導体装置の製造
方法を提供することにある。(4) Purpose of the Invention The purpose of the present invention is to eliminate this drawback, and as a result, eliminate the occurrence of abnormal diffusion regions caused by fine silicon (Si) powder adhering to the surface of a silicon (Si) substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that effectively prevents an increase in leakage current and has a good manufacturing yield.
(5) 発明の構成
本発明の構成は、シリコン（Si）基板を使用し
てなす半導体装置の製造方法において、素子形成
工程に先立ち、900〔℃〕以下の酸化性雰囲気中に
おいて熱処理を実行することを特徴とする、半導
体装置の製造方法にある。(5) Structure of the Invention The structure of the present invention is that in a method for manufacturing a semiconductor device using a silicon (Si) substrate, heat treatment is performed in an oxidizing atmosphere at a temperature of 900 [°C] or less prior to the element formation step. A method of manufacturing a semiconductor device is provided.
本発明の着想は、シリコン（Si）の酸化性雰囲
気中における酸化速度とシリコン（Si）への不純
物の拡散速度との差が、ある温度範囲において非
常に大きくなるという自然法則にもとづき、酸化
作用は発生するが不純物の拡散作用は発生しにく
い温度範囲すなわち900〔℃〕以下の比較的低い温
度範囲において、基板表面とそれに付着するシリ
コン（Si）微粉とを同時に酸化し、シリコン
（Si）微粉表面を、不純物拡散に対する阻止能力
のあるシリコン酸化膜（SiO2）をもつて覆うこ
とにより、続く拡散工程等における望ましくない
拡散を有効に防止することにある。 The idea of the present invention is based on the natural law that the difference between the oxidation rate of silicon (Si) in an oxidizing atmosphere and the diffusion rate of impurities into silicon (Si) becomes extremely large in a certain temperature range. Silicon (Si) fine powder is produced by simultaneously oxidizing the substrate surface and the silicon (Si) fine powder adhering to it at a relatively low temperature range of 900 [℃] or less, where impurity diffusion is difficult to occur. By covering the surface with a silicon oxide film (SiO 2 ) having the ability to prevent impurity diffusion, undesirable diffusion in the subsequent diffusion process and the like can be effectively prevented.
(6) 発明の実施例
以下、本発明の一実施例に係る半導体装置の製
造方法、特に、本発明の要旨である、シリコン
（Si）基板に対する熱処理方法について、説明し、
本発明の構成と特有の効果とを明らかにする。(6) Embodiments of the Invention Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention, in particular, a method of heat treatment for a silicon (Si) substrate, which is the gist of the present invention, will be explained.
The structure and unique effects of the present invention will be clarified.
シリコン（Si）ウエーハの表面に付着したシリ
コン（Si）微粉末のうち、比較的粒径の大きい、
例えば25〔μm〕程度以上のものを通常の方法を使
用して除去したのち、粒径の小さいものを除去す
ることを目的として以下の工程を実施する。シリ
コン（Si）ウエーハを酸化性の湿性酸素（O2）
雰囲気中で、900〔℃〕の温度において10分間熱処
理を実行し、シリコン（Si）ウエーハ表面に、厚
さ1000〔Å〕のシリコン酸化膜（SiO2）膜を形成
する。かかるシリコン酸化膜はその厚さの400〜
450〔Å〕が酸化前のシリコン基板表面よりシリコ
ン（Si）ウエーハ内に侵入して形成され、600〜
650〔Å〕が酸化前のシリコン基板表面より突出し
て形成される。この工程において、該シリコン
（Si）ウエーハ表面に付着した不純物を含有する
シリコン（Si）微粉末の表面も同時に酸化され、
厚さ1000〔Å〕のシリコン酸化膜（SiO2膜）で覆
われる。すなわち、該不純物を含有するシリコン
（Si）微粉末は、該シリコン酸化膜によつて包ま
れる。第１図は、本発明を実施する前のシリコン
（Si）ウエーハと、これに付着したシリコン微粉
末の状態を示す。同図において、１１はシリコン
（Si）ウエーハ、１２はシリコン微粉末である。
また第２図は、本発明にかかる酸化処理を施した
後の状態を示す。同図において１２′は残余のシ
リコン微粉末、１３は生成されたシリコン酸化膜
（SiO2膜）を示す。このような処理によつて続
く、酸化、拡散工程等においても、シリコン
（Si）微粉末からの不純物の異常拡散は検出され
ず、製造歩留りの向上に有効に寄与することが確
認された。 Among silicon (Si) fine powders attached to the surface of silicon (Si) wafers, relatively large particle size
For example, after particles of about 25 [μm] or larger are removed using a conventional method, the following steps are carried out for the purpose of removing particles with a small size. Silicon (Si) wafers are exposed to oxidizing wet oxygen (O 2 )
Heat treatment is performed in an atmosphere at a temperature of 900 [°C] for 10 minutes to form a silicon oxide (SiO 2 ) film with a thickness of 1000 [Å] on the surface of the silicon (Si) wafer. Such a silicon oxide film has a thickness of 400~
450 [Å] is formed by penetrating into the silicon (Si) wafer from the surface of the silicon substrate before oxidation;
650 [Å] is formed protruding from the surface of the silicon substrate before oxidation. In this step, the surface of the silicon (Si) fine powder containing impurities attached to the silicon (Si) wafer surface is also oxidized,
Covered with a 1000 Å thick silicon oxide film (SiO 2 film). That is, the silicon (Si) fine powder containing the impurity is surrounded by the silicon oxide film. FIG. 1 shows the state of a silicon (Si) wafer and silicon fine powder attached thereto before the present invention is implemented. In the figure, 11 is a silicon (Si) wafer, and 12 is silicon fine powder.
Moreover, FIG. 2 shows the state after performing the oxidation treatment according to the present invention. In the figure, reference numeral 12' indicates the remaining silicon fine powder, and reference numeral 13 indicates the produced silicon oxide film (SiO 2 film). Even in the oxidation, diffusion steps, etc. that follow such treatment, no abnormal diffusion of impurities from the silicon (Si) fine powder was detected, and it was confirmed that the process effectively contributes to improving the manufacturing yield.
(7) 発明の効果
以上説明せるとおり、本発明によれば、シリコ
ン（Si）基板表面に付着したシリコン（Si）微粉
末に起因する異常拡散領域の発生を伴わず、結果
として、リーク電流の増加等が有効に防止され、
製造歩留りが良好な半導体装置の製造方法を提供
することができる。(7) Effects of the Invention As explained above, according to the present invention, there is no abnormal diffusion region caused by silicon (Si) fine powder adhering to the silicon (Si) substrate surface, and as a result, leakage current is reduced. increase etc. is effectively prevented,
A method for manufacturing a semiconductor device with good manufacturing yield can be provided.
第１図は、本発明の実施前における半導体基板
表面の状態を示す断面図、第２図は本発明の実施
後の半導体基板の表面の状態を示す断面図であ
る。
１１…シリコン（Si）ウエーハ、１２…シリコ
ン微粉末、１３…シリコン酸化膜。
FIG. 1 is a sectional view showing the state of the surface of a semiconductor substrate before implementing the present invention, and FIG. 2 is a sectional view showing the state of the surface of the semiconductor substrate after implementing the present invention. 11... Silicon (Si) wafer, 12... Silicon fine powder, 13... Silicon oxide film.
Claims (1)
造方法において、素子形成工程に先立ち、900
〔℃〕以下の酸化性雰囲気中において熱処理を実
行することを特徴とする、半導体装置の製造方
法。[Claims] 1. In a method for manufacturing a semiconductor device using a silicon substrate, 900
A method for manufacturing a semiconductor device, characterized by performing heat treatment in an oxidizing atmosphere at [°C] or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113177A JPS594117A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57113177A JPS594117A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS594117A JPS594117A (en) | 1984-01-10 |
| JPH043661B2 true JPH043661B2 (en) | 1992-01-23 |
Family
ID=14605500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57113177A Granted JPS594117A (en) | 1982-06-30 | 1982-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594117A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2505273B2 (en) * | 1989-02-21 | 1996-06-05 | 信越半導体株式会社 | Silicon wafer donner killer heat treatment method |
| JP2571972B2 (en) * | 1990-02-08 | 1997-01-16 | 三菱マテリアル株式会社 | Manufacturing method of silicon wafer |
-
1982
- 1982-06-30 JP JP57113177A patent/JPS594117A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS594117A (en) | 1984-01-10 |
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