JPH04370600A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To test a row address buffer, a row decoder, a column address buffer, a column decoder and a bit line in a short time by reading out the memory cell test data of a memory cell array section. CONSTITUTION:The device has a first memory cell array section 1, which consists of plural EPROM cells 4 normally used as a memory and are placed in a matrix form, rows whose number it the same as the number of the array section 1 and bit number of row addresses A5, A4 and A3. The device also has a second memory cell array section 2 which has the row addresses A5, A4 and A3 information stored in EPROM cell 5 of each row, rows whose number is the same as the number of the bit number of column addresses A2, A1 and A0 an columns whose number is the same as the memory cell array section 1. The device also has a third memory cell array section 3 which has the column addresses A2, A1 and A0 information stored in EPROM cell 22 of each row and the stored data are read form the second and the third memory cell array sections 2 and 3. By making the above arrangements, testing cost is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having built-in memory cells for testing.

0002

2. Description of the Related Art Conventional semiconductor memory devices are not configured with memory cells for testing, and therefore, their operation tests are carried out by writing test data into memory cells that are normally used as memory. This is done by checking whether the written test data can be read out correctly.

0003

Here, the operation test of the semiconductor memory device is performed, for example, once before resin sealing and once after resin sealing. However, in recent years, the memory capacity of semiconductor memory devices has significantly increased, resulting in a significant increase in test time and an increase in test costs. For this reason, for example, after resin sealing, it is possible to suppress the increase in test time by conducting efficient tests on at least the row address buffer, row decoder, word line and column address buffer, column decoder, and bit line. is necessary.

For example, OTPROM (One Time
Programmable ROM (Programmable ROM) allows data to be written only once after resin sealing, so it is said that it is impossible to perform an operation test by writing test data. In order to improve the performance, it is required to be able to test at least row address buffers, row decoders, word lines, column address buffers, column decoders, and bit lines.

In view of the above, the present invention enables testing of row address buffers, row decoders, word lines and column address buffers, column decoders, and bit lines in a short time, thereby reducing test costs. In addition, when applying this especially to OTPROM, even after resin sealing, row address buffers, row decoders, word lines and column address buffers, column decoders,
An object of the present invention is to provide a semiconductor memory device in which bit line testing can be performed and reliability can be improved.

[0006]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a first memory cell array section in which a plurality of memory cells commonly used as a memory are arranged in a matrix, and a first memory cell array section. a second memory cell array section that is provided with the same number or fewer rows as the first memory cell array section and that shares a word line with the first memory cell array section and stores the first test data; The second memory cell array is provided with the same number of columns or a smaller number of columns as the memory cell array portion, and has bit lines in common with the first memory cell array portion.
and a third memory cell array section for storing test data.

[0007]

According to the present invention, by reading the test data of the memory cells in the second memory cell array section, the row address buffer, row decoder, and all or part of the word lines can be tested. Further, by reading the test data of the memory cells in the third memory cell array section, the column address buffer, column decoder, and all or some of the bit lines can be tested.

[0008]

[Embodiment] Hereinafter, with reference to FIGS. 1 to 9, the first embodiment of the present invention will be described.
Embodiments to Third Embodiments will be explained by taking as an example the case where the present invention is applied to an EPROM.

First Embodiment...FIGS. 1 to 7 FIG. 1 is a diagram showing the main parts of the first embodiment of the present invention.
L10 is a word line, BL0 to BL10 are bit lines, 1 is a first memory cell array section, 2 is a second memory cell array section, and 3 is a third memory cell array section.

The first memory cell array section 1 is a section normally used as a memory, and in this embodiment, 64 EPROM cells 4 are arranged in 8 rows and 8 columns. Therefore, in order to access the EPROM cell 4 of this memory cell array section 1, an address signal consisting of 6 bits is required. Now, let us assume that these address signals are A5, A4, A3, A2, A1, and A0.
64 EPROM cells 4 as shown in decimal numbers
An address of 0 to 63 is attached to the address signal A5 to A0.
When allocating A5 to A3 as row addresses and A2 to A0 as column addresses, the relationship between word lines WL0 to WL7 and row addresses A5 to A3 and bit lines BL0 to
The relationship between BL7 and column addresses A2 to A0 is also shown in binary numbers in FIG. 2.

Further, in FIG. 1, the second memory cell array section 2 is used for testing a row address buffer (not shown), a row decoder (not shown), and word lines WL0 to WL7. In the example, 24 EPROM cells 5 are arranged in 8 rows×8 rows as test memory cells.
They are arranged in three rows. As also shown in FIG. 1, address information for each row, that is, information on row addresses A5 to A3 for selecting the corresponding word lines WL0 to WL7, is stored in the EPROM cells 5 of each row.

Further, reference numerals 6, 7, and 8 are test bit line selection means for selecting bit lines BL8, BL9, and BL10, respectively, during testing. These test bit line selection means 6, 7, and 8 have the same circuit configuration, and the test bit line selection means 6 is representatively configured as shown in FIG. 3. . In the figure, 9 is the power supply voltage Vc
c, for example, a power line supplying a DC voltage of 5 [V], 10
is a DC voltage VHH higher than the power supply voltage Vcc, for example,
A VHH signal input terminal to which a signal consisting of a DC voltage of 7 [V] (hereinafter referred to as VHH signal) is input, 11 is a pMOS
, 12, 13, 14 are inverters, and in these inverters 12, 13, 14, 15, 16, 17 are p
MOS, 18, 19, and 20 are nMOS. Also, 2
1 is an nMOS forming a column gate.

In the test bit line selection means 6, when the bit line BL8 is not selected, the VHH signal is not input and the VHH signal input terminal 10 is set to L level. As a result, the output of inverter 12 becomes L level, the output of inverter 13 becomes H level, the output of inverter 14 becomes L level, and nMOS 21 is turned off. On the other hand, when the bit line BL8 is selected, the VHH signal is input, and the VHH signal input terminal 10 is set to 7 [V]. As a result, the output of inverter 12 becomes H level, the output of inverter 13 becomes L level, the output of inverter 14 becomes H level, and nMOS 21 is turned ON.

Further, in FIG. 1, the third memory cell array section 3 is used for testing a column address buffer (not shown), a column decoder (not shown), and bit lines BL0 to BL7. In the embodiment, 24 EPROM cells 22 are arranged in 3 rows x 8 columns as memory cells for testing. Similarly, as shown in FIG. 1, the EPROM cells 22 of each column store address information of each column, that is, information of column addresses A2 to A0 for selecting the corresponding bit lines BL0 to BL7.

Further, 23, 24, and 25 are test word line selection means for selecting word lines WL8, WL9, and WL10, respectively, during testing. These test word line selection means 23, 24, and 25 have the same circuit configuration, and the test word line selection means 23 is representatively configured as shown in FIG. 4. . In the figure, 2
6 is a power supply line that supplies the power supply voltage Vcc, 27 is a VHH signal input terminal to which a VHH signal is input, 28 is a pMOS,
29, 30, 31 are inverters, and in these inverters 29, 30, 31, 32, 33, 34 are pM
OS, 35, 36, and 37 are nMOS.

In the test word line selection means 23, when the word line WL8 is not selected, the VHH signal is not input and the VHH signal input terminal 27 is set to L level. As a result, the output of inverter 29 becomes L level, the output of inverter 30 becomes H level, the output of inverter 31 becomes L level, and word line WL8 becomes L level. On the other hand, when selecting word line WL8, V
The HH signal is input, and the VHH signal input terminal 27 is 7 [V
]. As a result, the output of inverter 29 is at H level, the output of inverter 30 is at L level, and inverter 31 is at
The output of the word line WL8 becomes H level, and the word line WL8 becomes H level.

Note that FIG. 5 shows the second memory cell array section 2.
6 is a sectional view taken along line AA in FIG. 5, and FIG. 7 is a sectional view taken along line BB in FIG. 5. In the figure, 38 is a P-type silicon substrate, 39 is an N+ diffusion layer that forms the source of the EPROM cell 5, and 40 is the EPROM cell 5.
N+ diffusion layer 41 (in FIG. 5,
42 is a contact hole; 43 is a silicon oxide film; 44 is a PSG film; 45 is a field oxide film;
is a P-type impurity to set the test data to "0".

[0018] Thus, in this first embodiment,
For the EPROM cell 5 that stores "0", a P-type impurity 46 is implanted into the channel region to turn it into an OFF state, but instead of this, only the memory cell that stores "1" is made into an EPROM cell. For example, for a memory cell that stores "0", a field oxide film 4
It is also possible to adopt a structure in which a floating gate and a word line are arranged above the gate electrode 5.

In the first embodiment configured as described above, a test can be performed, for example, as follows. First, a VHH signal is supplied to the test bit line selection means 8,
After selecting bit line BL10, word lines WL0 to WL
7 are activated in order to read data from the EPROM cell 5 connected to the bit line BL10. Next, the VHH signal is supplied to the test bit line selection means 7, and the bit line BL
After selecting bit line BL9, word lines WL0 to WL7 are activated in order to select EPROM cell 5 connected to bit line BL9.
Read the data. Next, test bit line selection means 6
After supplying the VHH signal to and selecting bit line BL8,
Activate word lines WL0 to WL7 in order to activate bit line BL.
The data of the EPROM cell 5 connected to the memory cell 8 is read out. Next, the VHH signal is supplied to the test word line selection means 25 to activate the word line WL10, and then the bit line B
L0 to BL7 are sequentially selected to read data from the EPROM cell 22 connected to the word line WL10. Next, the VHH signal is supplied to the test word line selection means 24,
After activating word line WL9, bit lines BL0 to BL
7 in order and the EPs connected to the word line WL9.
Read the data in the ROM cell 22. Next, the VHH signal is supplied to the test word line selection means 23, and the word line WL
After activating bit lines BL0 to BL7, EPROM cell 2 connected to word line WL8 is activated.
Read the data of 2.

Here, the test bit line selection means 8 selects VH.
After supplying the H signal and selecting bit line BL10, word lines WL0 to WL7 are activated in order to select bit line BL10.
In other words, when reading the data of the EPROM cell 5 connected to the
0→001→010→011→100→101→110
→111”, the output will be “0, 1, 0, 1
, 0, 1, 0, 1'', it can be determined that at least the address buffer for row address A3 is normal. This is because the address buffer for row address A3 is “0” regardless of whether row address A3 is “0” or “1”.
” (hereinafter, this failure state is referred to as the output “0” fixed state), even if the other parts are normal, the output will be “0, 0, 0, 0, 0. ,0,
0, 0", and the row address A3 becomes "0, 0".
A fault state in which only "1" is output, regardless of whether the output is "0" or "1" (hereinafter, this fault state is referred to as the output "1" fixed state)
If so, the output will be "1, 1, 1, 1, 1, 1, 1, 1" even if the other parts are normal.

[0021] Also, the test bit line selection means 7 has VHH.
After supplying a signal and selecting bit line BL9, word lines WL0 to WL7 are sequentially activated to read data from EPROM cell 5 connected to bit line BL9, that is, row addresses A5, A4, A3 "000→0
01→010→011→100→101→110→11
1”, the output will be “0, 0, 1, 1, 0,
0, 1, 1'', at least row address A4
It can be determined that the address buffer for This is because if the address buffer for row address A4 is in a fixed output state of "0", even if other parts are normal, the output will be "0, 0, 0, 0, 0, 0, 0, 0. ”
If the output is fixed at "1", the output will be "1, 1, 1," even if everything else is normal.
1, 1, 1, 1, 1".

[0022] Also, the test bit line selection means 6 has VHH.
After supplying a signal and selecting bit line BL8, word lines WL0 to WL7 are activated in order to read data from EPROM cell 5 connected to bit line BL8, that is, row addresses A5, A4, A3. "000→0
01→010→011→100→101→110→11
1”, the output will be “0, 0, 0, 0, 1,
1, 1, 1", at least row address A5
It can be determined that the address buffer for This is because if the address buffer for row address A5 is in a fixed output state of "0", even if other parts are normal, the output will be "0, 0, 0, 0, 0, 0, 0, 0. ”
If the output is fixed at "1", the output will be "1, 1, 1," even if everything else is normal.
1, 1, 1, 1, 1".

Furthermore, even if the address buffers for row addresses A5, A4, and A3 are normal, if the row decoder is not normal in the first place, the output from the EPROM cell 5 connected to the bit line BL10 will be "0". ,1,0
, 1, 0, 1, 0, 1", and the output from the EPROM cell 5 connected to the bit line BL9 is "0, 0,
1, 1, 0, 0, 1, 1" and the output from the EPROM cell 5 connected to the bit line BL8 is "0, 0.
, 0, 0, 1, 1, 1, 1".

In addition, the test bit line selection means 8 has VHH.
After supplying a signal and selecting bit line BL10, word lines WL0 to WL7 are activated in order to read data from EPROM cell 5 connected to bit line BL10, and the output is "0, 1, 0. ,1,0,1,0,
1,'' it can be determined that there is no short-circuit failure in the word lines WL0 to WL7. Because the word line WL
If there is a short circuit between 0 and WL7, for example, if word line WL0 and word line WL1 are shorted, the output will be "1 → 1 → 0 → 1 → 0 → 1 → 0 → 1". , "0"
This is because "1" is not output alternately.

In addition, the test word line selection means 25
After supplying the H signal and activating word line WL10, bit lines BL0 to BL7 are sequentially selected and word line WL10 is activated.
When reading the data of the EPROM cell 22 connected to the column address A2, A1, A0,
000→001→010→011→100→101→1
10 → 111", the output will be "0, 1, 0
, 1, 0, 1, 0, 1'', it can be determined that at least the address buffer for column address A0 is normal. This is because if the address buffer for column address A0 is in a fixed output state of "0", the output will be "0, 0, 0, 0, 0" even if other parts are normal.
, 0, 0, 0", and if the output is fixed at "1", even if other parts are normal,
This is because the output will be "1, 1, 1, 1, 1, 1, 1, 1".

In addition, the test word line selection means 24 has VH
After supplying the H signal and activating the word line WL9, bit lines BL0 to BL7 are sequentially selected to read data from the EPROM cell 22 connected to the word line WL9, that is, column addresses A2, A1 , A0 as “00
0→001→010→011→100→101→110
→111”, the output will be “0, 0, 1, 1
, 0, 0, 1, 1'', it can be determined that at least the address buffer for column address A1 is normal. This is because if the address buffer for column address A1 is in a fixed output state of "0", the output will be "0, 0, 0, 0, 0, 0" even if other parts are normal.
, 0, 0", and if the output is fixed at "1", even if other parts are normal, the output will be "1, 1, 1, 1, 1, 1, 1". , 1''.

In addition, the test word line selection means 23 has VH
After supplying the H signal and activating the word line WL8, bit lines BL0 to BL7 are sequentially selected to read data from the EPROM cell 22 connected to the word line WL8, that is, column addresses A2, A1 , A0 as “00
0→001→010→011→100→101→110
→111”, the output will be “0, 0, 0, 0
, 1, 1, 1, 1'', it can be determined that at least the address buffer for column address A2 is normal. This is because if the address buffer for column address A2 is in a fixed output state of "0", even if other parts are normal, the output will be "0, 0, 0, 0, 0, 0.
, 0, 0", and if the output is fixed at "1", even if other parts are normal, the output will be "1, 1, 1, 1, 1, 1, 1". , 1''.

Furthermore, even if the address buffers for column addresses A2, A1, and A0 are normal, in the first place,
If the column decoder is not normal, the output from the EPROM cell 22 connected to the word line WL10 will be “0,
1, 0, 1, 0, 1, 0, 1" and the word line WL
The output from the EPROM cell 22 connected to
0, 0, 1, 1, 0, 0, 1, 1", and the output from the EPROM cell 22 connected to the word line WL8 is "0, 0, 0, 0, 1, 1, 1, 1" will never occur.

In addition, the test word line selection means 25 has VH
After supplying the H signal and activating word line WL10, bit lines BL0 to BL7 are sequentially selected and word line WL1 is activated.
0, the output is "0, 1, 0, 1, 0, 1".
, 0, 1, 0, 1'', bit line BL0
~It can be determined that there is no short circuit failure in BL7. because,
If there is a short-circuited part among the bit lines BL0 to BL7, for example, if the bit line BL0 and bit line BL1 are short-circuited, the output will be "1 → 1 → 0 → 1 → 0 → 1 → 0 → 1 ”, and “0” and “1” are not output alternately.

As described above, according to the first embodiment, the row address buffer, row decoder, and word line can be tested by simply reading the test data from the memory cell array section 2. Column address buffers, column decoders, and bit lines can be tested simply by reading the test data in step 3. Therefore, row address buffers, row decoders, word lines, and column address buffers, column decoders, and bit lines can be tested. can be carried out in a short time, reducing test costs.

Second embodiment...FIG. 8 FIG. 8 is a diagram showing the main part of the second embodiment of the present invention.
Parts corresponding to those in the embodiment are given the same reference numerals. In this second embodiment, the second memory cell array section 2 has a configuration of 8 rows x 1 column, the third memory cell array section 3 has a configuration of 1 row x 8 columns, and the second and Test data as shown in FIG. 8 is stored in the EPROM cells 5 and 22 of the memory cell array sections 2 and 3 of No. 3. The rest of the structure is the same as that of the first embodiment. In addition, in the figure, "x" means arbitrary data of "1" or "0".

In the second embodiment configured as described above, a test can be performed, for example, as follows. First, the VHH signal is supplied to the test bit line selection means 6 to select the bit line BL8, and then the word lines WL0 to WL
7 is activated in order and connected to the bit line BL8.
Read the data of PROM cell 5. Next, the VHH signal is supplied to the test word line selection means 23, and the word line WL
After activating bit lines BL0 to BL7, EPROM cell 2 connected to word line WL8 is activated.
Read the data of 2.

Here, the test bit line selection means 6 selects VH.
After supplying the H signal and selecting the bit line BL8, the word lines WL0 to WL7 are sequentially activated and the output when reading data from the EPROM cell 5 connected to the bit line BL8 is "0, 1, 1. , 0, 1, ×, ×, ×”
In this case, it can be determined that the row address buffers and row decoders for row addresses A5, A4, and A3 are normal.

This is because, first, the word lines WL0, WL1
The fact that "0, 1" is output from the EPROM cell 5 connected to the row address means that the address buffer for row address A5 is fixed at output "0" and the address buffer for row address A4 is output "0". There is a possibility that the address buffer for row address A5 is in a fixed state with output "0", and that the address buffer for row address A5 is in a fixed state with output "1", and that the address buffer for row address A4 is in a fixed state with output "1". , the possibility that the address buffer for row address A5 is in a fixed output state of "0" and the address buffer for row address A4 is in a fixed state of output "1", and
There is no possibility that the address buffer for row address A5 has a fixed output of "1" and the address buffer for row address A4 has a fixed output of "0" (the address buffer for row address A5 has a fixed output of "0"). ” is in the fixed state and the address buffer for row address A4 is in the output “1” fixed state, row addresses A5, A4, A
If 3 is changed from "000 to 001", the row address actually accessed will be from "010 to 011", so the output will be "1, 0". Also, row address A5
address buffer is fixed at output “1”, and
If the address buffer for row address A4 is in a fixed output state of "0", row addresses A5, A4, and A3 are set to "0".
00 → 001'', the row address actually accessed will be ``100 → 101'', so the output will be ``1, ×''), and at least the address buffer for row address A3 will be It can be determined that it is normal (if the address buffer for row address A3 is in a fixed state of output "0", the output will be "0, 0" or "
×, ×”, and if the output is fixed at “1”, the output will be “1, 1” or “×, ×”).

If so, word line WL0
, WL1, WL2, and EPROM connected to WL3
The fact that "0, 1, 1, 0" is output from cell 5 means that the address buffer for row address A5 outputs "0, 1, 1, 0".
0" may be in a fixed state, but the row address A4
It can be determined that the address buffer for row address A4 is normal (the address buffer for row address A4 outputs "
0” fixed state, row addresses A5, A4, A3
If the row address is changed from 000 to 001 to 010 to 011, the row address actually accessed is from 000 to 0.
01→000→001", the output is "0, 1,
0, 1". Also, if the address buffer for row address A4 is in a fixed output state of "1", row addresses A5, A4, and A3 are set to "000→001→010→011".
”, the row address actually accessed will be “010→011→010→011”, so
The output will be "1, 0, 1, 0").

If so, word line WL0
, WL1, WL2, WL3, and E connected to WL4.
The fact that "0, 1, 1, 0, 1" is output from PROM cell 5 means that there is no possibility that the address buffer for row address A5 is in a fixed output state of "0" (the address for row address A5 is If the buffer output is fixed at “0”, row addresses A5, A4, A3 are changed from “000→0”.
01→010→011→100", the row address actually accessed is "000→001→100".
010→011→000", and the output is "0, 1, 1
, 0, 0''), it can be determined to be normal.

Furthermore, even if the address buffers for row addresses A5, A4, and A3 are normal, if the row decoder is not normal in the first place, the output from the EPROM cell 5 connected to the bit line BL8 will be "0". ,1,1,
0, 1, ×, ×, ×”. Further, in this case, at least the word line WL0 and the word line WL1
It can be determined that there is no short circuit between the word line WL2 and the word line WL3, and between the word line WL3 and the word line WL4.

In this way, when the data of the EPROM cell 5 connected to the bit line BL8 is read and the output is "0, 1, 1, 0, 1, ×, ×, ×", It can be determined that the row address buffers and row decoders for row addresses A5, A4, and A3 are normal.

In addition, the test word line selection means 23
After supplying the H signal and selecting the word line WL8, bit lines BL0 to BL7 are sequentially selected and the output when reading data from the EPROM cell 22 connected to the word line WL8 is "0, 1, 1, 0, 1, ×, ×, ×
'', it can be determined that the column address buffers and column decoders for column addresses A2, A1, and A0 are normal.

[0040] This is because, first, the bit lines BL0 and BL1
The fact that "0, 1" is output from the EPROM cell 22 connected to column address A2 means that the address buffer for column address A2 is fixed at output "0" and the address buffer for column address A1 is output "0". There is a possibility that the address buffer for column address A2 is in a fixed state with output "0", and that the address buffer for column address A2 is in a fixed state with output "1". , there is a possibility that the address buffer for column address A2 is in a fixed output state of "0" and the address buffer for column address A1 is in a fixed state of output "1", and that the address buffer for column address A2 is in a fixed state of output "1". 1” fixed state and column address A1
There is no possibility that the address buffer for column address A2 is in a fixed output state of "0" (the address buffer for column address A2 is in a fixed state of output "0", and the address buffer for column address A1 is in a fixed state of output "1"). In this case, if column addresses A2, A1, and A0 are changed from "000 to 001," the column address actually accessed will be from "010 to 011," so the output will be "1, 0." Furthermore, if the address buffer for column address A2 is in a fixed output state of "1" and the address buffer for column address A1 is in a fixed state of output "0", column addresses A2, A1, and A0 are changed to "000→001". ”, the column address actually accessed is “1”.
00 → 101", so the output is "1, ×")
In addition, it can be determined that at least the address buffer for column address A0 is normal (if the address buffer for column address A0 is in a fixed output state of "0", the output will be "0, 0" or " ×, ×”,
If the output is fixed at “1”, the output will be “1, 1” or “
×, ×”).

If so, bit line BL0
, BL1, BL2, and EPROM connected to BL3
The fact that "0, 1, 1, 0" is output from cell 22 means that the address buffer for column address A2 may be in a fixed output state of "0", but the address buffer for column address A1 is It can be determined that it is normal (if the address buffer for column address A1 is in a fixed state of output "0", column addresses A2, A
1. When A0 is changed as "000→001→010→011", the column address actually accessed is "
000→001→000→001", the output is "0, 1, 0, 1". Also, column address A1
If the address buffer for is fixed to output “1”,
Change row addresses A2, A1, A0 to “000→001→0
10 → 011", the column address actually accessed is "010 → 011 → 010 → 011".
”, so the output is “1, 0, 1, 0”).

If so, bit line BL0
, BL1, BL2, BL3, and E connected to BL4.
The fact that "0, 1, 1, 0, 1" is output from the PROM cell 22 means that there is no possibility that the address buffer for column address A2 is in a fixed output state of "0" (the address for column address A2 is If the buffer output is fixed at “0”, column addresses A2, A1, and A0 are set to “0”.
00 → 001 → 010 → 011 → 100", the column address actually accessed will be "000
→001→010→011→000", and the output is "
0, 1, 1, 0, 0), it can be determined that it is normal.

Furthermore, even if the address buffers for column addresses A2, A1, and A0 are normal, in the first place,
If the column decoder is not normal, the output from the EPROM cell 22 connected to the word line WL8 will be “0, 1”.
, 1, 0, 1, ×, ×, ×”. Also,
In this case, it can be determined that there is no short circuit at least between bit line BL0 and bit line BL1, between bit line BL2 and bit line BL3, and between bit line BL3 and bit line BL4. .

In this way, when the test data of the EPROM cell 22 connected to the word line WL8 is read, the output is "0, 1, 1, 0, 1, ×, ×,
In the case of "x", it can be determined that the address buffers and column decoders for column addresses A2, A1, and A0 are normal.

[0045] In this way, also in this second embodiment,
By simply reading the test data from the second memory cell array section 2, the row address buffer, row decoder, and some word lines can be tested. The column address buffer, column decoder, and some bit lines can be tested just by reading the . In addition, according to the second embodiment, the area of the second and third memory cell array sections 2 and 3 is larger than that of the first embodiment. can be made smaller.

Generally, the first memory cell array section 1 has rows from addresses 0 to 2n+1 (where n is an integer greater than or equal to 1), and rows from addresses 0 to 2m+1 (where m is an integer greater than or equal to 1). , the EPROM cells in the rows at addresses 0 and 3 in the second memory cell array section 2 store the same logic (for example, "0"), and the EPROM cells in the rows at addresses 1 and 2n store the same logic (for example, "0"). The cell stores a logic different from that of the EPROM cell 5 at addresses 0 and 3 (for example, "1"), and the same logic (for example, "0") is stored in the EPROM cell in the column at addresses 0 and 3. is stored in the EPROM cells in the columns 1 and 2m, and the EPROM cells in the columns 0 and 3.
By storing a different logic (for example, "1") than the cell 22, the test can be performed as described above.

Third Embodiment...FIG. 9 FIG. 9 is a diagram showing the main part of a third embodiment of the present invention. In this third embodiment, the first memory cell array section 1
The row addresses are 0, 1, 2, 3, and 4.
A row is provided only in the address row, and one EP is placed in each row.
The ROM cells 5 are arranged in one row, and the first
The column addresses of memory cell array section 1 are 0 and 1.
Columns are provided only in the columns of addresses 2, 3, and 4, and one EPROM cell 22 is arranged in each column in one row, and the second and third memory cell array sections 2 ,3
Test data as shown in FIG. 9 is stored in the EPROM cells 5 and 22 of the second embodiment, and the other configuration is the same as that of the second embodiment.

According to the third embodiment, as in the second embodiment, the tests of the row address buffer, row decoder, some word lines, column address buffer, column decoder, and some bit lines are shortened. In addition, according to the third embodiment, the EPROM of the second and third memory cell array sections 2 and 3 is more efficient than the second embodiment. The number of cells 5 and 22 can be reduced.

Generally, the first memory cell array section 1 has rows from addresses 0 to 2n+1 and rows from addresses 0 to 2m+1.
When providing columns of addresses, rows are provided in the second memory cell array section 2 only at the rows of addresses 0, 1, 3, and 2n in the row address of the first memory cell array section 1. , one EPROM cell is arranged in each row in one column, and as test data, the EPROM cells at addresses 0 and 3 in the row address of the first memory cell array section 1 are used as test data.
The same logic (for example, "0") is stored in the M cells, and the row addresses 1 and 2 of the first memory cell array section 1 are stored.
The EPROM cell at address n stores a different logic (for example, "1") from the EPROM cells at addresses 0 and 3 at the row address of the first memory cell array section 1, and the third memory cell array section 3 stores a different logic (for example, "1"). , first memory cell array section 1
A column is provided only in the column address 0, 1, 3, and 2m in the column address, and each column has one EPR.
The OM cells are arranged in one row, and the column address of the first memory cell array section 1 is set to 0 as test data.
The EPROM cell at address 3 has the same logic (for example,
"0") is stored in the EPROM cells at addresses 1 and 2m in the column address of the first memory cell array section 1.
The logic (for example, "
1)).

In the above embodiment, the memory cells provided in the second and third memory cell array sections 2 and 3 are
Although the case has been described in which it is configured with PROM cells, mask ROM cells or the like may be used instead.

[0051] In the above embodiment, the case where the present invention is applied to an OTPROM has been described;
The present invention applies to mask ROM, DRAM, SRAM, EEP
ROM, etc., is configured by arranging memory cells in rows and columns.
It can be applied to any semiconductor memory device, but especially when applied to OTPROM, it can be used to create row address buffers, row decoders, word lines, and Column address buffers, column decoders, and bit lines can be tested, improving reliability.

[0052]

As described above, according to the present invention, by reading the test data of the memory cells in the second memory cell array section, the row address buffer, row decoder, all or some of the word lines can be Also, by reading the test data of the memory cells in the third memory cell array section, the column address buffer, column decoder, and all or part of the bit lines can be tested. , row address buffers, row decoders, word lines, column address buffers, column decoders, and bit lines can be tested in a short time, reducing test costs. Especially when applied to OTPROMs, After sealing with resin, it is possible to perform tests on row address buffers, row decoders, word lines and column address buffers, column decoders, and bit lines, which have not been possible until now, thereby improving reliability. Can be done.

[Brief explanation of drawings]

FIG. 1 is a diagram showing main parts of a first embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between word lines and row addresses and the relationship between bit lines and column addresses in the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing test bit line selection means constituting the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing test word line selection means constituting the first embodiment of the present invention.

FIG. 5 is a plan view showing a portion of the second memory cell array section.

6 is a sectional view taken along line AA in FIG. 5. FIG.

7 is a sectional view taken along line BB in FIG. 5. FIG.

FIG. 8 is a diagram showing main parts of a second embodiment of the present invention.

FIG. 9 is a diagram showing main parts of a third embodiment of the present invention.

[Explanation of symbols]

1 First memory cell array section 2 Second memory cell array section 3 Third memory cell array section

Claims (4)

[Claims] 1. A first memory cell array section in which a plurality of memory cells commonly used as a memory are arranged in rows and columns; A second memory cell array section that is provided to share a word line with the memory cell array section and stores the first test data; 1. A semiconductor memory device comprising a memory cell array section and a third memory cell array section that shares a common bit line and stores second test data. 2. The second memory cell array section has the same number of rows as the first memory cell array section and the same number of columns as the number of bits of a row address for selecting the rows of the first memory cell array section. and storing information of the row address in the memory cells of each row as the first test data, and the third memory cell array section is for selecting a column of the first memory cell array section. has the same number of rows as the number of bits of the column address and the same number of columns as the first memory cell array section, and stores information on the column address in the memory cells of each column as the second test data. 2. The semiconductor memory device according to claim 1, further comprising a semiconductor memory device. 3. The second memory cell array section has the same number of rows and 1-bit columns as the first memory cell array section, and the second memory cell array section has the same number of rows and one-bit columns as the first memory cell array section, and the second memory cell array section has the same number of rows and 1-bit columns as the first memory cell array section. The same logic is stored in the memory cells at addresses 0 and 3 at the row address of , and the same logic is stored in the memory cells at addresses 1 and 2n (where n = an integer greater than or equal to 1) at the row address of the first memory cell array section. A different logic is stored in the memory cells at row addresses 0 and 3 in the first memory cell array section, and the third memory cell array section
It has a row of 1 bit and the same number of columns as the first memory cell array section, and as the second test data, the first
The same logic is stored in the memory cells at addresses 0 and 3 in the column address of the first memory cell array section, and the same logic is stored in the memory cells at addresses 1 and 2m in the column address of the first memory cell array section (however, m
= an integer of 1 or more) stores a logic different from that of the memory cells at addresses 0 and 3 in the column address of the first memory cell array section.
The semiconductor storage device described above. 4. The second memory cell array section is a portion of the row of the first memory cell array section at row addresses 0, 1, 3, and 2n (where n = an integer greater than or equal to 1). has only one row and one memory cell in each row.
The same logic is stored as the first test data in the memory cells at addresses 0 and 3 in the row address of the first memory cell array section. The memory cells at addresses 1 and 2n (where n is an integer of 1 or more) at the row address of are stored with different logic from the memory cells at addresses 0 and 3 at the row address of the first memory cell array section. The third memory cell array section has column addresses 0, 1, 3, and 2m (however, m
= an integer greater than or equal to 1), and one memory cell is arranged in each column so as to form one row, and the first memory is used as the second test data. The same logic is stored in memory cells at addresses 0 and 3 in the column address of the cell array section, and memories at addresses 1 and 2m (where m = an integer of 1 or more) in the column address of the first memory cell array section. 2. The semiconductor memory device according to claim 1, wherein the cell stores logic different from memory cells at addresses 0 and 3 in the column address of the first memory cell array section.