JPH04372164A - Manufacture of bicmos semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate an electrode forming step and to prevent etching damage of an emitter-base by selectively growing a polycrystalline semiconductor layer, and implanting an impurity by using an ion implantation at the time of forming source-drain high concentration layer of NMOS, PMOS transistors. CONSTITUTION:A thick element isolating oxide film 36 is selectively formed on surfaces of an NMOS Tr forming region 34a, a PMOS Tr forming region 33a, an element isolating region and an N-N-P Tr forming region 33b. A thick oxide film 42 is formed between an emitter region and a base leading region of the region 33b. Then, gate electrodes 48, 49, a collector electrode 50, a base electrode 51 and an emitter electrode 52 are formed. After an oxide film 57 is formed on an entire surface, sidewalls 58 are formed on the sidewalls of the electrodes by etching. Further, As is ion implanted to form source-drain high concentration layer 61 in the region 34a by As ion implanting, and N-type impurity is simultaneously implanted in the electrodes 48, 50, 52.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a BMOS transistor having a bipolar transistor and a CMOS transistor on the same substrate.
The present invention relates to a method for manufacturing an i-CMOS type semiconductor device.

0002

[Background Art] In recent years, in order to pursue high-speed CMOS, Bi CMOS hybrid technology has been widely used, which aims to increase the speed by forming bipolar elements on the same chip and increasing the load driving ability of CMOS with bipolar. It's starting to look like this.

Generally, since Bi CMOS LSI combines the characteristics of bipolar and CMOS, it can achieve excellent performance such as high speed, high integration, high voltage resistance, high load driving ability, and low power consumption. requires epitaxial layers and isolation diffusion to mount bipolar elements. In addition, in order to simultaneously form bipolar and CMOS devices without sacrificing their performance, the process is complicated and the number of masks increases, but this is disadvantageous from an economic standpoint, so we try to minimize the number of steps during the process. need to be designed.

A conventional method for manufacturing a Bi CMOS type semiconductor device will now be described with reference to FIG. First, Figure 7(a)
As shown in the figure, after forming an N+ buried diffusion layer 2 and a P+ buried diffusion layer 3 on a P-type semiconductor substrate 1, a thickness of 2 μm is formed.
N- epitaxial layer 4, followed by selective diffusion to P
A well layer 5 and a separation diffusion layer 6 are formed simultaneously. After that, a thin oxide film 7 of about 500 Å and a thickness of 1600 Å are formed on the entire surface of the substrate.
After forming the nitride film 8 to a certain extent, the nitride film 8 in the device isolation region is selectively removed as shown in the figure. Further, a resist pattern 9 is formed, and using the resist pattern 9 as a mask, a P-type impurity such as B (boron) is implanted into the channel stopper region of the NMOS Tr and the surface region of the isolation diffusion layer 6 by ion implantation. Furthermore, N-type impurities are also implanted into the channel stopper region of the PMOS Tr using a similar method.

[0005] Here, the N+ buried diffusion layer 2 is NPN
In order to lower the collector series resistance of the Tr (bipolar Tr), As (arsenic) and Sb (antimony) are used in the NPN Tr formation region to form a resistance of 20 to 100 Ω/□, and to prevent the PMOS Tr from causing parasitic bipolar operation. It is also formed in the PMOS Tr formation region at the same time. On the other hand, the P+ buried diffusion layer 3 is NPN Tr
It is formed in advance in the element isolation region by ion implantation, etc., and is used to shorten the isolation and diffusion time by utilizing upward diffusion from the semiconductor substrate 1 during the next epitaxial process or isolation diffusion. , 50-30 using B
It is set to 0Ω/□, and is also formed at the same time in the NMOS Tr formation region so that the NMOS Tr does not cause parasitic bipolar operation. In addition, the N- epitaxial layer 4 has device characteristics of NPN Tr and PMOS.
The concentration and thickness are determined so that the gate threshold voltage of Tr can be controlled. Furthermore, P-
The isolation diffusion layer 6 and the P-well layer 5 are formed by diffusion from the surface of the epitaxial layer 4 in order to control the element isolation of the NPN Tr and the threshold voltage of the NMOS Tr.

Next, after removing the resist pattern, 900
As shown in FIG. 7(b), a thick oxide film 10 for isolation is formed by oxidation treatment at a temperature of approximately .degree. C., and at the same time,
Activate the ion-implanted impurities to form NMOS Tr
A channel stopper layer 11 of PMOS Tr and a channel stopper layer 12 of PMOS Tr are formed.

After that, known diffusion, photolithography, and etching are repeated to form a PMOS as shown in FIG. 7(c).
Tr, NMOS Tr, and NPN Tr are formed to complete the Bi CMOS structure. To explain this simply, first, the base region 13 of NPN Tr
form. Next, PMOSTr and NMOSTr
A gate oxide film 14 and a gate electrode 15 are formed. Next, the source/drain region 16 of the PMOS Tr
and NPN Tr base extraction region 17 are formed at the same time. Finally, the source/drain region 18 of the NMOS Tr, the emitter region 19 of the NPN transistor, and the collector extraction region 20 are simultaneously formed.

[0008]

[Problems to be Solved by the Invention] The above is a bipolar T
r and a normal MOS Tr are manufactured on the same substrate as Bi CMOS, but the normal MOS Tr
As miniaturization progresses, deterioration of characteristics due to hot carriers is inevitable. Therefore, in ordinary fine CMOS type semiconductor devices, LDD (Lightly Do
In recent years, MOS transistors have been formed in a drain structure. However, MOS with LDD structure
When attempting to manufacture Tr and bipolar Tr on the same substrate, the following problems occurred.

■ Complicated process The LDD structure MOS transistor itself has a very complicated process, and there is also a high-performance bipolar transistor in it.
Attempting to incorporate this will further complicate the process and result in a low yield of the product. It also leads to an increase in manufacturing costs.

■ Etching damage to emitter and base When a Bi CMOS structure is formed using an LDD structure,
During the anisotropic etching performed when forming the sidewalls, the base region is also etched, and the etching damage causes an adverse effect on the bipolar transistor (such as an increase in emitter-base leakage current).

The present invention has been made in view of the above points, and eliminates the problems of complicating the process and etching damage to the emitter and base, and improves the LDD structure CMOS.
It is an object of the present invention to provide a method for manufacturing a BiCMOS type semiconductor device in which a Tr and a bipolar Tr can be manufactured on the same substrate.

0012

[Means for Solving the Problems] In the present invention, a polycrystalline semiconductor layer is selected on the NMOS and PMOS transistor gate regions, the bipolar transistor collector extraction region, the base extraction region, and the emitter region of a semiconductor substrate. When forming highly doped source and drain layers of LDD structure NMOS and PMOS transistors, impurities are introduced into these polycrystalline semiconductor layers using ion implantation for forming the highly doped layers. Furthermore, during etching for sidewall formation, the surface of the bipolar transistor formation region of the semiconductor substrate is covered with the polycrystalline semiconductor layer and the thick oxide film.

[0013]

[Operation] In the above invention, a polycrystalline semiconductor layer is selectively grown, and NMOS, PMO, etc. are added to the polycrystalline semiconductor layer.
By introducing impurities using ion implantation when forming the source/drain heavily doped layers of an S transistor, NMOS can be manufactured using the same polycrystalline semiconductor and without an etching process.
, the gate of the PMOS transistor, and the collector, base, and emitter electrodes of the bipolar transistor are formed.

Furthermore, during etching for sidewall formation, since the surface of the bipolar transistor formation region of the semiconductor substrate is covered and protected by the polycrystalline semiconductor layer and the thick oxide film, no etching damage occurs to the bipolar transistor formation region. I won't join.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. First, specific resistance 15Ω・cm, surface orientation <1
As shown in FIG. 1(a), an N+ buried layer 31 with a sheet resistance of 30 Ω/□ and a junction depth of about 4.5 μm is formed on a P-type substrate (not shown) of 00> with Sb as an impurity. Next, a P+ buried layer 32 with a sheet resistance of 300 Ω/□ and a junction depth of about 1.3 μm is formed on the same substrate using boron as an impurity. Subsequently, an N-type epitaxial layer having a resistivity of 5 Ω·cm and a thickness of about 2 μm is formed on the entire surface of the substrate by a known epitaxial technique. Then, in this N type epitaxial layer, an N well layer 33 is formed above the N+ buried layer 31.
Then, a P well layer 34 is formed above the P+ buried layer 32. Here, the N-well layer 33 is formed as a PMOS Tr formation region and an NPN Tr (bipolar Tr) formation region, and hereinafter the N-well layer 33 in the PMOS Tr formation region will be referred to as a PMOS Tr formation region and will be denoted by the reference numeral 33a. , the N well layer 33 in the NPNTr formation region is referred to as the NPNTr formation region, and the reference numeral 33
Add b. Further, the P well layer 34 is an NMOS Tr.
It is formed as a formation region and an element isolation region.
Below, the P well layer 34 in the NMOSTr formation region is made of NMO.
The P well layer 34 in the element isolation region is hereinafter referred to as the element isolation region and is designated by the symbol 34a as the S Tr formation region.
Add 4b. Note that the P+ buried layer 32 under the element isolation region 34b also functions as an element isolation region.

Next, a heavily doped N+ region 35 is formed in a part of the NPN Tr formation region 33b, as shown in FIG. 1(b), for the purpose of lowering the collector resistance of the NPN Tr. This N+ region 35 is formed if necessary.

Next, using the well-known LOCOS isolation technique, an NMOS Tr formation region 34 is formed as shown in FIG. 1(c).
a surface, the surface of the PMOS Tr formation region 33a,
A film with a thickness of 4000 to 7000 Å is selectively formed on the surface of the element isolation region 34b and the surface of the NPN Tr formation region 33b.
A thick element isolation oxide film 36 is formed. At this time, NPN
On the surface of the Tr formation region 33b, the thick element isolation oxide film 36 is also formed between the base region and the collector extraction region.

Next, a resist and the element isolation oxide film 3 are formed on the base region portion of the NPN Tr formation region 33b.
6 as a mask, a base region (P-type diffusion layer) 37 is formed in a self-aligned manner as shown in FIG. 2(a). After that, a gate oxide film 38 with a thickness of 160 to 250 Å is formed on the exposed surface of each region 34a, 33a, and 33b, and then the gate oxide film 38 is formed into an NPN film as shown in FIG. 2(b).
It is removed from the surface of the Tr formation region 33b, and the NMOS
The gate oxide film 38 is left only on the surface of the Tr formation region 34a and the PMOS Tr formation region 33a.

Thereafter, as shown in FIG. 2(c), a polysilicon film 39 is formed on the entire surface to a thickness of about 500 Å using a known LD-CV method.
After forming a thin oxide film (not shown) on the surface using the D method, a SiN film 40 having a thickness of about 1500 Å is formed on the entire surface using the CVD method. And this SiN
The film 40 is made of NPN using photolithography and etching technology.
An opening 41 is formed in a portion between the emitter region and the base extraction region of the Tr formation region 33b. After the opening 41 is formed, thermal oxidation is performed in a wet O2 atmosphere at 900° C. for about 15 minutes using the SiN film 40 as a mask, thereby forming the emitter region as shown in FIG. 3(a). The polysilicon film 39 between the base extraction regions is converted into a thick oxide film 42 of about 1000 Å.

After that, after removing the entire SiN film 40,
As shown in FIG. 3(b), an oxide film 4 is formed using a known low-temperature CVD method.
3 is formed to a thickness of about 4000 Å over the entire surface. Then, the NMOS Tr formation region 34a and the PMOS
On the gate region portion of the Tr formation region 33a and on the NP
Openings 44 are opened above the collector extraction region, the base extraction region, and the emitter region of the N Tr formation region 33b. Then, if necessary, MOS
A diffusion layer 45 for controlling the channel concentration of the Tr, and a diffusion layer (base extraction region 46) for lowering the resistance of the base extraction region of the NPN Tr.
is formed in each region 34a, 33a, 37 by ion implantation. Incidentally, the base extraction region 46 is originally created later by impurity diffusion from the polysilicon film, but if the impurity concentration is desired to be higher, it is preliminarily created by ion implantation at the stage shown in FIG. 3(b). .

Next, using the oxide film 43 as a mask, the opening 44 is formed integrally with the polysilicon film 39 using a known CVD process.
Using a technique, polysilicon 47 is selectively grown at 850° C. and 170 Å/min as shown in FIG. 3(c).
Gate electrodes 48, 49 of NMOS Tr and PMOS Tr and collector electrode 50 of NPN Tr
, a base electrode 51, and an emitter electrode 52 are formed.

Next, after removing the oxide film 43 by a known etching technique as shown in FIG. 4(a), the oxide film 43 is removed as shown in FIG.
), the area other than the NMOS Tr formation region 34a is covered with a resist 53, and phosphorus ions are implanted at an acceleration voltage of 80 KeV and a dose of 5E12 ions/cm, for example.
By performing this process at a concentration of about 2.0 nm, a low concentration layer (n- layer) 54 of the source and drain of the NMOS Tr is formed in the NMOS Tr formation region 34a. Next, similarly, Figure 4
As shown in (c), the PMOS Tr formation region 33a
The area other than the top is covered with a resist 55, and boron ions are implanted at an acceleration voltage of 80 KeV and a dose of 1E13 ions, for example.
/cm2, a low concentration layer (P- layer) 56 of the source and drain of the PMOS Tr is formed in the PMOS Tr formation region 33a.

Thereafter, using the known CVD technique, the image forming process shown in FIG. 5 (
After forming the oxide film 57 on the entire surface as shown in FIG.
Sidewalls 58 are formed on the sidewalls 0, 51, and 52. At this time, the polysilicon film 39 is also patterned so as to remain only at each electrode portion. Below, each electrode 48,
49, 50, 51, and 52, including the remaining polysilicon film 39, are called electrodes. Also, during this etching, NMOS
In the Tr formation region 34a and the PMOS Tr formation region 33a, the gate oxide film 38 is etched except for the gate electrode portion, and the surfaces of each region 34a and 33a (Si surface) are exposed. On the other hand, since the NPN Tr forming region 33b is protected by the thick electrode polysilicon and the thick oxide films 36 and 42, the surface of the region 33b (
(Si surface) is not exposed. Note that the sidewall 58 may be formed of a polysilicon film instead of the oxide film.

Next, NMOS and PMOS Tr
After forming an oxide film 59 with a thickness of about 200 Å on the exposed surfaces of the forming regions 34a and 33a as shown in FIG. 5(c), as shown in FIG. 50,
Cover the area other than 52 with resist 60, and apply As to acceleration voltage 50
By implanting ions at KeV and a dose of 2E16 ions/cm2, the NMOS Tr formation region 3 is formed.
4a, a high concentration layer (n+ region) 61 for the source and drain of the NMOS Tr is formed, and at the same time the NMOS Tr
N-type impurities are introduced into the gate electrode 48 of the Tr 2 and the collector electrode 50 and emitter electrode 52 of the NPNTr 2 . By introducing this impurity, the polysilicon electrode 48,
50 and 52 have low resistance and function as electrodes, and the collector electrode 50 and emitter electrode 52 serve as impurity diffusion sources for forming a collector extraction region and an emitter region, which will be described later.

Next, as shown in FIG. 6(a), PM
On the OS Tr formation region 33a and the NPN Tr
By covering the area other than the base electrode 51 with a resist 62 and implanting BF2 ions at an acceleration voltage of 70 KeV and a dose of about 3E15 ions/cm2, a PMOS Tr is formed in the PMOS Tr formation region 33a.
High concentration layer of source/drain of Tr (P+ region)
At the same time, P-type impurities are introduced into the gate electrode 49 of the PMOS Tr and the base electrode 51 of the NPN Tr in order to lower the resistance and serve as an impurity diffusion source.

[0026] Thereafter, in an N2 atmosphere at 900°C, 3
Anneal for about 0 minutes. By this annealing, the impurities in the high concentration layers 61 and 63 are activated, and at the same time, the impurities are diffused from the emitter electrode 52, base electrode 51, and collector electrode 50, and as shown in FIG.
A collector extraction region 64 is formed in the formation region 33b, and a base extraction region 46 and an emitter region 65 are formed in the base region 37. Note that if the base extraction region 46 has been preliminarily created at the stage of FIG. 3(b), it will be completed to a predetermined high concentration by the impurity diffusion in FIG. If the formation in step 3 is omitted, it is formed for the first time in FIG. 6(b). After that, normal wiring formation is performed, and the entire process is completed.

[0027]

As described above in detail, according to the present invention, a polycrystalline semiconductor layer is selectively grown, and ions are implanted into the polycrystalline semiconductor layer when forming high-concentration layers for sources and drains of NMOS and PMOS transistors. Since impurities are introduced using the same polycrystalline semiconductor, the gate electrodes of NMOS and PMOS transistors and the collector, base, and emitter electrodes of bipolar transistors can be formed using the same polycrystalline semiconductor and without an etching process. The process becomes easier, so even if the MOS transistor has an LDD structure, a Bi CMOS device can be manufactured without complicating the process. Furthermore, during etching for sidewall formation, the surface of the bipolar transistor formation region of the semiconductor substrate is protected by the polycrystalline semiconductor layer and the thick oxide film, and no etching damage is applied to the bipolar transistor formation region. This prevents deterioration of the characteristics of bipolar transistors.

Further, if the above-mentioned electrode formation method is used as in the embodiment, and a plurality of regions of the bipolar transistor are formed by impurity diffusion from the electrode, the complexity of the process can be further avoided. In terms of the number of masks used in photolithography to avoid complicating the process, according to the example, the manufacturing method for a normal LDD structure CMOS requires 3 masks, or in some cases 2 masks.
(One sheet when forming the base region 37 in FIG. 2(a), one sheet when forming the opening 41 in FIG. 2(c),
(If one is added when forming the N+ region 35 in b), the total becomes three.) By just adding one, the MOS transistor can be converted into an LDD.
A Bi CMOS device with this structure can be manufactured.

Furthermore, as in the embodiment, by selectively oxidizing the polysilicon film on the surface of the substrate, a thick oxide film (oxide film 42 in FIG. 3A) for preventing etching damage was formed between the emitter region and the base extraction region. ), it becomes possible to form the thick oxide film without adversely affecting the base region already formed in the substrate. Furthermore, the emitter region and the base lead-out region, which will be formed later, are self-aligned with this oxide film, and there is no need to consider photolithography margin between the emitter and base lead-out regions, so that the bipolar transistor can be downsized.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 2 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 3 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 4 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 5 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 6 is a process sectional view showing a part of an embodiment of the present invention.

FIG. 7 is a process sectional view showing a conventional manufacturing method.

[Explanation of symbols]

33a PMOS Tr formation region 33b NP
NTr formation region 34a NMOS Tr formation region 36 Element isolation oxide film 42 Oxide film 47 Polysilicon 48 Gate electrode 49 Gate electrode 50 Collector electrode 51 Base electrode 52 Emitter electrode 54 Low concentration layer 56 Low concentration layer 57 Oxide film 58 Sidewall 61 High concentration layer 63 High concentration layer

Claims (1)

[Claims] [Claim 1] NMOS and PMOS of semiconductor substrate
A polycrystalline semiconductor layer as each electrode is selectively grown on the transistor gate region, the bipolar transistor collector extraction region, the base extraction region, and the emitter region, and other parts of the bipolar transistor formation region of the same substrate. The process involves obtaining a structure covered with a thick oxide film, and forming an NMOS transistor and a PM in the substrate.
After sequentially forming the low concentration layers of the source and drain of the OS transistor, a sidewall forming film is deposited on the entire surface of the substrate and etched to form a film on the sidewall of the polycrystalline semiconductor layer serving as the electrode. Step of forming sidewalls and then NMOS transistor and PMO
A Bi CMOS type semiconductor device comprising the steps of sequentially implanting impurity ions for forming high concentration layers of the source and drain of an S transistor, and simultaneously introducing impurities into a polycrystalline semiconductor layer as each electrode. Production method.