JPH04372216A - peak hold circuit - Google Patents

Abstract

PURPOSE:To improve a conventional peak holding circuit which has been used for the inspection of a high voltage power supply or the like and unable to be applied only to a signal waveform whose frequency is below that determined by the time constant of components so that the circuit can be appliesd even to a signal waveform whose frequency is high. CONSTITUTION:A ramp waveform generating section 7 which produces a ramp waveform resulting from a reference voltage changed lineraly hourly and an input signal terminal 8 receiving an input signal are connected to a voltage comparator 9, and the voltage comparator 9 compares a ramp waveform with an input signal waveform and outputs a timing signal to a peak holding section 10 when the input signal waveform whose level is over the ramp waveform is received to allow the section 10 to hold the voltage of the ramp waveform.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit for holding the peak of a voltage waveform used for testing multi-output power supplies.

0002

2. Description of the Related Art A conventional peak hold circuit is constructed as shown in FIG. In Fig. 5, 1 is an input signal terminal, 2 is an operational amplifier for a buffer to lower the output impedance of the signal source, 3 is a diode for half-wave rectification, and 4 is a diode for half-wave rectification.
5 is an operational amplifier that senses the voltage held by the capacitor 4 with a high input resistance, and 6 is an output terminal.

With this configuration, when a positive input signal waveform is input to the positive terminal of the buffer operational amplifier 2 via the input signal terminal, the operational amplifier 2 becomes a positive output and is applied to the anode of the diode 3. When the voltage held in the capacitor 4 connected to the cathode side of the diode 3 is lower than the output voltage of the operational amplifier 2, the capacitor 4 is charged through the diode 3. Since the voltage charged in the capacitor 4 is fed back to the negative terminal of the operational amplifier 2 through the operational amplifier 5, the voltage input to the positive terminal of the operational amplifier 2 is held and output. Furthermore, if the voltage signal waveform input to the positive terminal of operational amplifier 2 is lower than the voltage held so far or is a negative voltage signal waveform, charging through diode 3 is not performed, so operational amplifier 5 The output retains its previous state.

0004

[Problems to be Solved by the Invention] In such a conventional peak hold circuit, when the input voltage becomes high frequency due to the reduction in the capacitor 4 and the time constant of the output resistance of the operational amplifier 2 and the internal resistance of the diode 3, the capacitor 4 is not charged. A lack of time occurs and an error occurs as shown in FIG.

Generally, the capacitor 4 has a small capacity to cope with high frequency signal waveforms, but this has the disadvantage that the stability of the hold voltage at the capacitor 4 deteriorates. This is because there is a leakage current from the cathode of the diode 3 to the output of the operational amplifier 2 and the positive terminal of the operational amplifier 5 to the ground, which causes the capacitor 4 to discharge. Therefore, only signal waveforms with a frequency lower than the frequency determined by the time constant of the components of the peak hold circuit can be stably held at their peak.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a peak hold circuit which eliminates the above-mentioned conventional drawbacks and is capable of stably holding peaks even in high frequency signal waveforms.

[0007]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a voltage comparison between a ramp waveform generator that creates a ramp waveform by linearly changing a reference voltage, and an input signal terminal to which an input signal is applied. This voltage comparator compares the ramp waveform and the input signal waveform, and when there is an input signal waveform that is greater than or equal to the ramp waveform, a timing signal is applied to the peak hold section to hold the voltage of the ramp waveform. This is what I did.

[0008]

[Operation] With the above configuration, the peak hold section itself does not require high frequency responsiveness, and stable peak hold can be realized regardless of the frequency band of the input signal waveform.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A peak hold circuit according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

First, in FIG. 1, reference numeral 7 denotes a ramp waveform generator that generates a ramp waveform by linearly varying the reference voltage;
8 is an input signal terminal to which an input signal is applied; 9 is a voltage comparator that compares the ramp waveform and the input signal waveform and issues a timing signal when there is an input signal waveform greater than or equal to the ramp waveform;
Reference numeral 10 designates a peak hold section that holds the voltage of the ramp waveform according to the timing signal, and reference numeral 11 represents an output terminal.

[0011] The operation of the above configuration will be explained as follows.
At the same time that the input signal to be measured is applied to the input signal terminal 8, a ramp waveform that changes at a constant slope is applied from the ramp waveform generating section 7 to the peak hold section 10 and the voltage comparator 9. The voltage comparator 9 compares the input signal waveform to be measured and the ramp waveform, and outputs a hold timing signal to the peak hold unit 10 when the voltage of the input signal waveform to be measured exceeds the voltage of the ramp waveform. The peak hold section 10 holds the ramp waveform voltage from the ramp waveform generation section 7 in accordance with the timing signal of the voltage comparator 9.

As a specific example, the peak level of the ripple noise waveform included in the DC power output waveform shown in FIG. 2 was measured. The ripple noise waveform has a frequency of several megahertz, and by setting the slope of the ramp waveform in accordance with the generation interval of the ripple noise waveform, a stable peak hold circuit with a frequency characteristic of 20 MHz can be obtained.

Next, another embodiment will be explained using FIGS. 3 and 4. As shown in FIG. 3, the ramp waveform generators are divided into a plus ramp waveform generator 7a and a minus ramp waveform generator 7
The voltage comparators are also divided into a positive voltage comparator 9a and a negative voltage comparator 9b so that waveforms are applied from the input signal terminal 8 and from the positive and negative ramp waveform generators 7a and 7b, respectively. Positive voltage comparator 9a
, the outputs of the negative voltage comparator 9b are connected to a positive peak hold section 10a and a negative peak hold section 10b, respectively.
When the voltages of the input signal waveforms on the positive side and negative side of the measurement target become equal to or higher than the voltage of the ramp waveform, the ramp waveform voltage from the ramp waveform generators 7a and 7b is held. 12 is an operational amplifier that measures the difference between the positive and negative peak-held voltages.

As shown in FIG. 4, each of the plus and minus circuits performs peak hold at each voltage polarity, and the operational amplifier 12 outputs the difference between the two input voltages, so that peak-to-peak voltage measurement can be performed.

[0015]

[Effects of the Invention] Since the peak hold circuit of the present invention is configured as described above, it is possible to measure high frequency signal waveforms with high precision, such as ripple noise measurement of switching power supplies that have become higher in frequency in recent years, and minute spike-like high frequency noise. This means that it can be easily detected and is of great industrial value.

[Brief explanation of drawings]

[Fig. 1] A block diagram showing an embodiment of the peak hold circuit of the present invention.

[Figure 2] Diagram of the measured waveform and peak-held output waveform of the same circuit

[Figure 3] Block diagram of another embodiment

[Figure 4] Measurement target waveform and peak held output waveform diagram of the same example

[Figure 5] Block diagram of conventional peak hold circuit

[Figure 6
】The same conventional measurement target waveform and output waveform diagram with peak hold

[Explanation of symbols]

7 Ramp waveform generation section 7a Plus ramp waveform generator 7b Negative ramp waveform generator 8 Input terminal 9 Voltage comparator 9a Positive voltage comparator 9b Negative voltage comparator 10 Peak hold section 10a Plus peak hold part 10b Minus peak hold section 11 Output terminal 12 Operational amplifier

Claims (2)

[Claims] Claim 1: A ramp waveform generator that generates a ramp waveform by linearly changing a reference voltage, and an input signal terminal to which an input signal is applied, are connected to a voltage comparator, and the voltage comparator generates a ramp waveform and an input signal. A peak hold circuit configured to compare waveforms and apply a timing signal to a peak hold section when there is an input signal waveform greater than or equal to a ramp waveform, and to hold the voltage of the ramp waveform by this peak hold section. 2. The peak hold circuit according to claim 1, further comprising an operational amplifier which separates the ramp waveform generating section, the voltage comparator, and the peak hold section into a plus side and a minus side, and measures the voltage difference between the two peak hold sections.