JPH0437632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image recording device suitable for displaying still moving images such as those on a television screen or recording them on other recording media.

In this type of still image recording device, when a moving image that moves like a television screen is frozen at a certain frame, the still image may blur, or even if there is no blur, it may freeze at an inappropriate scene. Therefore, there are many problems when using the screen unless you monitor the stationary screen. Also, when re-recording a still screen from frame memory to another recording medium such as a disk or tape, due to the difference in conversion speed between the two (for example, frame memory is 1/60 seconds, tape is 2 to 4 seconds). During the data transfer period, it is necessary to notify the end of recording using an indicator lamp, buzzer, etc.

Therefore, in the past, as a countermeasure against screen blur when the screen is still, it is not sufficient to use only the static screen, which tends to cause blurring, so if a static screen is not appropriate, cancel this, create a video, and then freeze the screen again to create an appropriate still image. To achieve this, three buttons were used: pause, release, and start. Therefore, such a configuration has disadvantages such as complicated handling and complicated configuration. In addition, displaying the time difference between data transfer between the frame memory and other recording media using a lamp or using a buzzer has the disadvantage that it is cumbersome to use, as it is necessary to confirm the time difference each time.

This invention has been made in view of this point, and provides a still image that can reliably and quickly obtain a desired still image without blur by simply operating a single button while watching a television screen. The present invention provides a recording device.

Hereinafter, one embodiment of the present invention will be described in detail based on the accompanying drawings.

In the figure, 1 is a stationary operation button switch, and 2 is a flip-flop circuit. As the flip-flop circuit 2, for example, an R-S flip-flop circuit consisting of NAND circuits 2a and 2b is used, and one input of the NAND circuit 2a is used. The end is connected to contact terminal a of switch 1, and NAND circuit 2
One input end of the switch b is connected to the contact b side of the switch 1. The other input end of the NAND circuit 2a is connected to the output side of the NAND circuit 2b.
The other input terminal of is connected to the output side of the NAND circuit 2a. The common terminal c of the switch 1 is grounded. Note that the switch 1 is normally closed to the contact A side, and when the switch 1 is pressed to obtain a still image, it is connected to the contact B side, and when the pressure is released, the switch returns to the contact A side. ing.

The output side of the flip-flop circuit 2, that is, the output side of the NAND circuit 2a, is connected to one input terminal of a NOR circuit 3, and the output side of the NOR circuit 3 is connected to a clock terminal CK of a D-type flip-flop circuit 4. The inverting output terminal of the flip-flop circuit 4 is connected to its own input terminal D and also to one input terminal of an AND circuit 5. The output side of the AND circuit 5 is connected to the input terminal D of the D-type flip-flop circuit 6, and the output side of the AND circuit 5 is connected to the input terminal D of the D-type flip-flop circuit 6.
CK is connected to terminal 7 and also to one input end of OR circuit 8. A pulse (frame pulse) synchronized with one frame of an image is supplied to the terminal 7. Further, the output terminal Q of the flip-flop circuit 6 is connected to one input terminal of an AND circuit 9, and the other input terminal of the AND circuit 9 is configured to receive a write pulse to be supplied to a frame memory (not shown). ing. A terminal 11 for controlling write/read of the frame memory is taken out from the output side of the AND circuit 9, and when the output of the output terminal Q of the flip-flop circuit 6 is at a high level (H), a write pulse from the terminal 10 is sent to the terminal 11. is supplied to the frame memory via the output terminal Q of the flip-flop circuit 6.
When the output of is at low level (L), the AND circuit 9 closes the gate and no write pulse is supplied from the terminal 11 to the frame memory. That is, at this time, only a read operation is performed on the frame memory, and the frame memory is set in a still mode in which a still image can be obtained.

Further, the output terminal Q of the flip-flop circuit 6 is connected to the clear terminal CLR of the counter 12. This counter 12 is cleared when the level of the clear terminal CLR is high level, and is placed in a counting state when the level of the clear terminal CLR is low level. The output side of the counter 12 is connected to the other input terminal of the OR circuit 8, the other input terminal of the NOR circuit 3, and further connected to the input terminal B of the monostable multivibrator 13.
When the pulse applied to the input terminal B rises from a low level to a high level, this multivibrator 13 generates a recording start signal that falls from a high level to a low level at its inverted output terminal. The time period during which this start signal is at a low level, that is, the width of the output pulse, is determined by the values of the capacitor c and resistor R connected to the terminals T ₁ and T ₂ .

Further, the output side of the OR circuit 8 is connected to the clock terminal CK of the counter 12. The counter 12 stops counting after counting a predetermined number of frame pulses (approximately 16 _ns x 2) from the terminal 7, for example 32 (approximately 1 second), and outputs a high level signal to its output side. Therefore, this counter 12
When the output becomes high level, the OR circuit 8 stops supplying the frame pulse from the terminal 7. That is, when the level of one input terminal of the OR circuit 8 is at a high level, the output side of the OR circuit 8 is at a high level regardless of the level of the frame pulse from the terminal 7, and the counter 12 is in a clear state. Similarly, when the output of the counter 12 becomes high level, the other input terminal of the NOR circuit 3 becomes high level, so that regardless of the level of the pulse supplied from the flip-flop circuit 2 to one input terminal of the NOR circuit 3. , the output side of the NOR circuit 3 becomes low level. In other words, NOR circuit 3 is counter 1
When the output of switch 2 becomes high level, the gate is substantially closed and the operating state of switch 1 is no longer accepted. 14 is an output terminal connected to the inverted output terminal of the multivibrator 13, and when the output of the counter 12 becomes high level, the data recorded in the frame memory is transferred from this output terminal 14 to another recording medium. A start signal is generated indicating that the data may be transferred to.

Reference numeral 15 is a terminal to which an end signal indicating that recording from the frame memory to another recording medium has been completed is supplied to the monostable multivibrator 1.
It is connected to input terminal A of 6. This multivibrator 16 is opposite to the multivibrator 13 described above, and when the end signal applied to the input terminal A falls from a high level to a low level, an output pulse that falls from a high level to a low level is sent to the inverting output terminal. Occur. The width of this output pulse is also determined by the values of the capacitor c and resistor R connected to the terminals T ₁ and T ₂ . The inverting output terminal of the multivibrator 16 is connected to one input terminal of an AND circuit 17, the output side of the AND circuit 17 is connected to the reset terminal R of the flip-flop circuit 4, and the other input terminal of the AND circuit 17 is connected to the reset terminal R of the flip-flop circuit 4. Reset signal from terminal 18 when power is turned on (low level)
are being supplied. Therefore, the flip-flop circuit 4 is reset when the power is turned on, and when the end signal is supplied from the frame memory to the terminal 15, it is reset by the output (low level) of the inverting output terminal of the multivibrator 16. The flip-flop circuit 4 is reset by this end signal, thereby releasing the static mode state. Further, the other input terminal of the AND circuit 5 and the reset terminal R of the multivibrators 13 and 16 are connected to the power supply terminal +Vcc via a resistor so as to normally be at a high level, and positive power is supplied from this. .

Next, the operation of this circuit will be explained. If the switch 1 is now pressed to switch from the contact a side to the contact b side, the output side of the flip-flop circuit 2 will accordingly change from high level to low level. The other input side of the NOR circuit 3 on the output side of the flip-flop circuit 2 is normally at a low level. Therefore, when the output side of the flip-flop circuit 2 becomes low level, the level on the output side of the NOR circuit 3 is changes from low level to high level. The level of the inverting output terminal of the flip-flop circuit 4 is normally at a high level. Therefore, when the output of the NOR circuit 3 goes from a low level to a high level, the level at the output side of the flip-flop circuit 4 changes from a high level to a low level.

When the output of the inverting output terminal Q of the flip-flop circuit 4 becomes low level, the output of the AND circuit 5, which is normally at a high level, becomes a low level. A low level output is sent out in synchronization with the frame pulse. This closes the gate of the AND circuit 9, and the supply of the write pulse supplied from the terminal 10 to the frame memory is stopped. In other words, the operating mode becomes a static mode. The above operation is repeated every time the switch 1 is pressed within a predetermined period of time after entering the rest mode, that is, until the counter 12 finishes counting 32 frame pulses. In other words, a torge operation is performed. Therefore, by repeating the freeze and release operations while pressing switch 1 within a predetermined period of time, and stopping the operation of switch 1 when the desired still image is obtained, the operation mode can be changed to frame mode as shown below. The operation begins to transfer the data in the memory to another recording medium.

Now, after performing the toggle operation as described above, when the output of the output terminal of the flip-flop circuit 6 becomes low level, the counter 12 enters a counting state and starts counting the frame pulses supplied from the terminal 7 through the OR circuit 8. When this counter 12 counts a predetermined number of frame pulses, for example 32 in this case, its output level becomes high level. This causes the counter 12
is in a clear state and no longer receives frame pulses supplied from terminal 7 through OR circuit 8. In other words, counting of frame pulses is stopped. At the same time, the output side of the counter 12 becomes high level, so that the level of the other input terminal of the NOR circuit 3 becomes higher than the low level, so that the gate of the NOR circuit 3 is substantially closed. , by pressing switch 1, the pulses supplied from flip-flop circuit 2 are no longer supplied to flip-flop circuit 4. In other words, approximately 1 second after entering the stationary mode (counter 3
Responsible for counting 32 frame pulses in step 2), torge operations will no longer be accepted. At the same time, a start signal for transferring the data recorded in the frame memory to another recording medium is outputted from the multivibrator 13 via the output terminal 14. During this time, write pulses to the frame memory are prohibited and the state is in static mode, so
When the start signal is generated, transfer from the frame memory to another recording medium begins, and at this time, no operation of switch 1 is accepted as described above.

When the data transfer to another recording medium is completed, an end signal is supplied from the frame memory to the terminal 15, which causes the multivibrator 1
6 and the AND circuit 17, the flip-flop circuit 4 is reset and the static mode is released.
The next switch 1 operation will be accepted.

As described above, according to the present invention, if the still mode is not canceled within a predetermined time after entering the still mode, data is transferred from the frame memory to another recording medium, so that the TV screen is By simply operating a single button switch while viewing the screen, a desired still image can be obtained, and the still image can also be reliably and quickly transferred to and recorded on other recording media such as a disk or tape.

In the above-described embodiment, the static mode may be canceled as necessary until the end signal is supplied after a predetermined period of time has elapsed. A release operation button switch for resetting may be provided. Further, the count number of the counter 12, that is, the predetermined time after the torg operation is not limited to the above-mentioned value, and can be arbitrarily set as necessary.

[Brief explanation of drawings]

The figure is a circuit configuration diagram showing an embodiment of the present invention. 1 is an operation button switch, 2 is an R-S flip-flop circuit, 3 is a NOR circuit, 4 and 6 are D-type flip-flop circuits, 5 and 9 are AND circuits, 8 is an OR circuit, 12 is a counter, and 13 and 16 are monostable. It is a multi-vibrator.

Claims (1)

[Scope of Claims] 1. A still image recording device that stores data for one frame of a moving image in a frame memory and then transfers the data to another recording medium for recording, comprising: a switch for instructing still image operation; In response to the first operation of the switch, data for one frame of the video is stored in the frame memory, and a control signal is generated to hold the data stored in the frame memory. memory control means for generating a control signal for canceling data retention in the frame memory; means for detecting the elapse of a predetermined time since the first switch operation; A still image recording apparatus comprising: recording control means for generating a recording start signal for transferring data held in the frame memory to the other recording medium in response to detection.