JPH0437676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a servo circuit that controls the rotation of a motor, and more particularly to a digital servo circuit that obtains error information as a digital ramp output using a measurement counter.

Generally, servo circuits that control the rotation of a motor obtain an error output by comparing a feedback signal corresponding to the motor's rotational speed and rotational phase with a reference signal, and use this error output to control the rotation. There is. As the feedback signal, for example, the first
As shown in the figure, a general rotation control circuit for a motor 1, by operating a frequency generator 2 and a pulse generator 3 according to the rotation of the motor 1, a frequency signal _FG proportional to the rotation speed of the motor 1 is obtained. At the same time, a phase pulse φ _PG indicating the rotational phase of the motor 1 is obtained. The speed servo circuit 4 to which the frequency _FG is supplied has a reference frequency V _REF indicating the target rotational speed. A speed control signal is generated according to the difference frequency from the frequency _FG . Further, the phase servo circuit 5 to which the phase pulse φ _PG is supplied performs a phase comparison between the standard pulse φ _REF indicating the reference rotational phase and the phase pulse φ _PG , and forms a phase control signal according to the phase difference. do. A rotation control signal is obtained by combining the speed control signal and the phase control signal in a signal adder 6, and the operation of the motor drive circuit 7 is controlled using this rotation control signal, thereby controlling the motor 1 to achieve the desired speed. Rotate at the rotational speed and locked to the reference phase.

FIG. 2 is a block diagram showing the basic structure of a general digital servo circuit used as the servo circuit described above. That is, in FIG. 2, the flip-flop circuit 11 triggered by the reference signal S _REF and the return signal S _FB forms a measuring window pulse having a pulse width proportional to the phase error of each of the signals. And the measurement counter 14
By counting the clock pulses supplied from the clock generator 12 via the NAD gate circuit 13 which is gate-controlled by the measurement wind pulse, the count output digitally indicating the phase error is converted into digital/analog. 15. The digital/analog converter 15 converts the digital phase error information from the measurement counter 14 into analog information and outputs a control signal. That is, the measurement counter 14 outputs digital information corresponding to an analog lap indicating a phase error as shown in FIG. 3 by counting clock pulses gated with the pulse width of the measurement window pulse. The amplitude of the lamp output shown in FIG. 3 corresponds to the dynamic range of the servo circuit, and the time axis range corresponds to the lock range. Therefore, in a digital servo circuit using the measurement counter 14, in order to increase the clock frequency to perform finer quantization and to ensure the same time axis (lock) range, the bits of the measurement counter 14 must be increased. We have to increase the number. Furthermore, even if the clock frequency is the same and the time axis (lock) range is lengthened, the number of bits must be increased.

By the way, for example, if a rotating magnetic head device is used,
The phase servo of the drum motor in an NTSC video tape recorder has a 30°
A phase reference signal φ _REF of Hz is used, and its lamp output also has a standard cycle of 30 Hz. Then, set the lock range to approximately 1/10 of the repetition period of 1/30 sec of the lamp output _lA .
In other words, it is set to about 3.3ms. here,
The slope of the lamp output, the dynamic range, and _the time axis range are set by taking into consideration the conditions of the entire motor rotation control system. In this case,
With a lamp output _lB with a narrow dynamic range, the gain of the servo system becomes high, which tends to result in an oscillatory control state, and there is a large possibility that it will deviate from the lock range due to disturbances. There is a problem that the lamp output L _C with a wide range has a low gain and a slow response speed. Furthermore, even if the optimum lamp output _lA is used, in a steady state in which the servo system is actually in phase lock, it is sufficient to respond to fluctuations of approximately 10% or less of the lock range; is not used.

Therefore, in view of the above-mentioned problems with conventional digital servo circuits, the present invention provides a new configuration in which a measurement counter with a small number of bits can secure a lock range and can also provide sufficient quantization accuracy in a steady state. This is a digital servo circuit.

Hereinafter, one embodiment of the digital servo circuit according to the present invention will be described in detail with reference to the drawings.

The embodiment shown in the block diagram of FIG. 5 is one in which the present invention is applied to the phase servo circuit in the above-mentioned motor control circuit, and the number of pulses is determined according to the phase error between the phase pulse φ _PG and the phase reference signal φ _REF . 7-bit measurement counter 2 that counts the clock pulses of
4, and a 7-bit memory counter 25 for counting the 1/8 frequency-divided output of the clock pulse.

The measurement counter 24 is supplied with clock pulses of a number corresponding to the phase error from the clock pulse generator 22 via the NAD gate circuit 23. That is, the AND gate circuit 23 performs gate control using a wind pulse for measuring the pulse width corresponding to the phase error formed by the flip-flop circuit 21 triggered by the phase pulse φ _PG and the phase reference signal φ _REF . As a result, a number of clock pulses corresponding to the phase error are supplied to the measurement counter 24.

The measurement counter 24 is
By counting the clock pulses supplied via the AND gate circuit 23, a count output indicating the phase error as 7-bit digital data is obtained, and this count output is converted into digital data via the first signal selection circuit 31. - Supplies the analog converter 26. Further, the measurement counter 24 has its third
A bit output, that is, a 1/N frequency divided output that is output once every eight clock pulses are counted, is supplied to the memory counter 25 via the second signal selection circuit 32.

Further, the memory counter 25 counts the 1/8 frequency-divided output of the clock pulse, obtains a count output indicating a phase error as 7-bit digital data, and sends this count output to the servo state detection circuit 41.
and the first signal selection circuit 31
The signal is supplied to the digital-to-analog converter 26 via.

The analog output obtained from this digital-to-analog converter 26 is supplied to the first and second hold circuits 51 and 52 via the third signal selection circuit 33. And each of the above hold circuits 51, 52
The hold outputs of the buffer amplifiers 53,
The signal is supplied to a signal adder 55 through 54, and output from the signal adder 55 as a servo control signal.

Here, the first to third signal selection circuits 3
1, 32, 33 are the servo state detection circuits 41
The operation is controlled in the following manner by a control circuit 42 that operates in response to the detection output.

That is, the servo state detection circuit 41 detects whether or not the servo system is in a locked steady state. Then, until the motor is started and the servo system is pulled into the lock state, the measurement counter 2
The clock pulse whose frequency is divided by 1/8 by 4 is counted by the memory counter 25, and the memory counter 25
The counting output from the digital-to-analog converter 26
Each signal selection circuit 31, 32,
The selection operation of 33 is controlled by a control circuit 42.
This operating state is shown in FIG.

That is, until the servo system is pulled into the lock range, the count output from the memory counter 25 is used as phase error information. Since this memory counter 25 forms a clock pulse whose frequency is divided by 1/8 in the measurement counter 24, it has a wide lock range _L1 as shown by the solid line in FIG.
phase error information can be given.

Then, by controlling the pull-in operation of the servo system using the count output of the memory counter 25 as control data, the servo system enters a locked steady state, and at the same time, the memory counter 25 stores the count contents at that time. In this steady state, the count output from the measurement counter 24 and the memory contents of the memory counter 25 are alternately supplied to the digital-to-analog converter 26 via the first signal switching circuit 31. The memory counter 25 provides DC bias data of the servo system in a steady state. And the measurement counter 24
gives phase error information in a narrow lock range _L2 , as shown by the broken line in FIG.

Here, the servo state detection circuit 41 detects the count output (from 00000000 to
1111111) wide lock range L ₁ given as
The servo system locks the state in which the phase error information within falls within the desired phase error range set for the servo system (the narrow lock range L ₂ given as the count output (0000000 to 1111111) by the measurement counter 24). It is detected as a steady state.

Further, a servo control signal obtained by converting the count output from the memory counter 25 into an analog signal by the digital-to-analog converter 26 is sent to the hold circuit 5.
The gain of the buffer amplifier 53 supplied through the hold circuit 52 is determined by the servo control signal obtained by converting the count output from the measurement counter 24 into an analog signal by the digital-to-analog converter 26.
The gain is set to eight times the gain of the buffer amplifier 54 supplied through the buffer amplifier 54.

Therefore, in this embodiment, the memory counter 2
If the phase servo is applied to the lamp output in the wide lock range _L1 given by 5 and the motor is locked at point A in FIG. 6, then the value of the memory counter 25 corresponding to the drive voltage _V By memorizing the counting contents and driving the motor with the drive voltage V _B corresponding to the lamp output in the narrow lock range L ₂ given by the measurement counter 24 and the above drive voltage V _A , the result shown in FIG. Phase lock will be applied at point B. Here, since the purpose of the phase servo system is to lock the phase at a certain point within a predetermined lock range, the measuring counter 24 with a small number of bits, The memory counter 25 and the digital-to-analog converter 26 control the pull-in operation of the servo system over a wide lock range, and in a steady state, it is possible to perform highly accurate phase servo control with little quantization error.

In addition, in the above-mentioned embodiment, each counter 24, 2
Although the 7-bit phase error information output from 5 is converted into an analog signal by the digital-to-analog converter 26, the phase error information can also be treated as a pulse width modulation signal as in the embodiment shown in FIG.

That is, in the embodiment shown in FIG. 7, the count output from a measurement counter 64 for counting clock pulses is supplied to a ring counter 66 for pulse width modulation, and this ring counter remotely converts the clock pulses into a pulse width modulation signal. Phase error information is sent to filter 8
1 to the signal adder 83. Further, the memory counter 62 counts the clock pulses whose frequency has been divided by 1/8 by the measurement counter 64, and
By operating a ring counter using the counted contents as a preset, phase error information is converted into a pulse width modulation signal and output. This pulse width modulated signal is supplied to a signal adder 83 via a filter 82. The memory counter 65 is selectively supplied with the pulse width modulation clock signal φ _PWM and the clock pulse whose frequency has been divided by 1/8 by the measurement counter 64 via the signal selection circuit 70. . In this embodiment as well, servo control operations similar in principle to the embodiment shown in FIG. 5 described above are performed.

That is, the pull-in operation of the servo system is controlled using the phase error information given as a pulse width modulation signal from the memory counter 65 as control data, and in a steady state, the pulse width modulation signals from each counter 64 and 65 are added and combined. The servo system can be controlled with high precision using data.

As described above, according to the present invention, the first N clock pulses are counted according to the error information.
A bit counter, a second N-bit counter that counts the 1/M frequency-divided output of the clock pulse by the first N-bit counter, and a servo system locked based on the counting output from the second N-bit counter. A servo state detection circuit that detects whether or not the servo state is in a steady state, and a control circuit that controls switching of the operation of the servo system based on the detection output of the servo state detection circuit, and the second N-bit counter The retracting operation of the servo system is controlled using the counting output as control data, and in a steady state where the servo system is locked, the first and second N
By controlling the operation of the servo system using control data obtained by combining the outputs of each count from the bit counter, the servo system can be pulled in over a wide lock range, achieving high precision with little quantization error in steady state. Digital servo control can be performed, and moreover, the digital servo control can be performed using a counter with a small number of bits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a general motor rotation control circuit. FIG. 2 is a block diagram showing a conventional example of a digital servo circuit. FIGS. 3 and 4 are explanatory diagrams of the lamp output according to the phase error information in the conventional example.
FIG. 5 is a block diagram showing an embodiment of the digital servo circuit according to the present invention. FIG. 6 is an explanatory diagram for explaining the operation of the above embodiment. FIG. 7 is a block diagram showing another embodiment of the digital servo circuit according to the present invention. 21...Flip-flop circuit, 22...Clock pulse generation circuit, 23...AND gate circuit,
24, 25, 64, 65, 66...Counter, 2
6...Digital-to-analog converter, 31, 32,
33, 70... Signal switching circuit, 41... Servo state detection circuit, 55, 83... Signal adder.

Claims (1)

[Claims] 1. A first N-bit counter 24, 64 that counts clock pulses with a number of pulses depending on error information.
and a second N-bit counter 25, 65 that counts the 1/M frequency-divided output of the clock pulse by the first N-bit counter, and the servo system is locked based on the counting output from the second N-bit counter. a servo state detection circuit 41 for detecting whether or not the servo state detection circuit is in a steady state; and a control circuit 42 for controlling switching of the operation of the servo system based on the detection output from the servo state detection circuit; The pull-in operation of the servo system is controlled using the counting output from the bit counter as control data, and in a steady state where the servo system is locked, the servo system is controlled using control data obtained by combining each counting output from the first and second N-bit counters. A digital servo circuit characterized by controlling motion.