JPH0437934A - Address conversion circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to reduce power consumption, reduce the mounting area, and facilitate LSI integration with regard to address conversion circuits necessary for rearranging the order of data. In an address translation circuit that generates a write address and a read address, a first counter generates a cyclical upper address in its enabled state, and a first counter generates a cyclical lower address in its enabled state. a second counter;
A first selector that outputs the first counter hay enable signal, a first selector that outputs the second counter hay enable signal, and outputs of the first and second counters both reach a maximum value. detecting that the first
and a decoding/switching means for controlling both the second selector to switch from one selection to the other selection, and the first selector is connected to the ripple carry output of the 20th counter and the ripple carry output of the 20th counter. the second selector receives the tenth signal at its input terminal;
The ripple carry output of the counter and the always-enabled signal are received at the input terminals, one of the first and second selectors selects the always-enabled signal, and the other selects the always-enabled signal.
The ripple carry output of the one selector is selected.

[Industrial application field]

The present invention relates to an address conversion circuit necessary for rearranging the order of data.

For example, a digital color image data signal consisting of a luminance signal and three types of color difference signals for each pixel is processed in separate filter circuits, so the data order is different. is required to be rearranged.

Additionally, image data and the like are generally required to undergo vertical and horizontal conversion.

[Prior art and problems to be solved by the invention] Part 8
The figure shows the configuration of a conventional address conversion circuit. In FIG. 8, 30 is a write address generation counter, 31 is an address conversion ROM 132 is a selector, and 33 is a write address generation counter.
is a RAM, and 34 is a data register.

At the timing when input data is written to the RAM 33, the selector 32 is controlled so that the cyclic address generated by the write address generation counter 30 is directly supplied to the RAM 33. Also, RAM33
At the timing when data is read from the ROM 31, the cyclic address generated by the write address generation counter 30 is converted into an address in the ROM 31, and the selected one is selected by the selector 32 and supplied to the RAM 33. In this way, by converting the write address and read address to the RAM 33, the order of the data is rearranged.

However, in the conventional configuration described above, since the conversion is performed using a ROM, there are problems in that power consumption is large and the mounting area is also large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an address conversion circuit that consumes less power, has a small mounting area, and is easily integrated into an LSI.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of an address conversion circuit that generates a write address and a read address for data into a memory according to the present invention. In FIG. 1, ■ is a first counter, 2 is a second counter, 3 is a first selector, 4 is a second selector, and 5 is a decoding/switching means.

The first counter 1, in its enabled state,
Generates a circular upper address.

The second counter 2, in its enabled state,
Generates circular low-order addresses.

The first selector 3 outputs the first counter 1 hay enable signal.

The first selector 4 outputs the second counter 2 enable signal.

The decoding/switching means 5 detects that the outputs of the first and second counters 1 and 2 have both reached the maximum value, and switches both the first and second selectors 3.4 from one selection to the other. control to switch to the selection.

The first selector 3 receives the ripple carry output of the 20th counter 2 and an always-enable signal at its input terminal, and the second selector 4 receives the ripple carry output of the first color counter 1. and an always-enable signal at the input terminals of the first and second selectors 3.
One of the four selectors selects the always-enabled signal, and the other selects the ripple carry output of the one selector.

[Operation] When the first selector 3 selects the ripple carry output of the second counter 2 and the second selector selects the always enabled signal, the lower bits of the address are synchronized with a clock (not shown). The count of the second counter 2 that outputs increases cyclically, and each time the count of the second counter 2 reaches the maximum value and the ripple carry output becomes valid, the first counter that outputs the upper bit of the address increases cyclically. The count of the counter is incremented. Thus, in such a selected state, the upper bits of the address are counted up each time the lower bits of the address reach the maximum value. That is, the addresses as a whole increase cyclically.

In this way, when the counts of the first and second counters 1.2 both reach the maximum value, the decoding/switching means 5
The selection of the first and second selectors 3.4 above is
The selector 3 selects the always enabled signal, and the second selector selects the ripple carry output of the first counter 1.

In this switched state, the first counter 1 that outputs the upper bits of the address is always enabled, so the count of the first counter l that outputs the upper bits of the address in synchronization with the above clock is The count of the second counter 2, which increases cyclically and outputs the lower bits of the address, is incremented each time the count of the first counter 1 reaches the maximum value and the ripple carry output becomes valid. Thus, in such a selected state, the address output from the address conversion circuit of FIG.
The second counter 2 changes intermittently by the maximum value (one count of the first counter 1) and outputs the lower bit of the address each time the output of the first counter 1 reaches the maximum value. The count is incremented.

For example, as shown in Fig. 2, the count range of the first counter 1 is plotted as 0 to 3 on the vertical axis, and the count range of the second counter 2 is plotted as C-F (hexadecimal) on the horizontal axis. Then, in the former selection state mentioned above, addresses will be output in order from the first column to the second column on the left of the grid in Fig. 2, and on the other hand, in the latter selection state mentioned above, In the selected state, from the first row to the second row on the grid in FIG.
The addresses will be output in the order of the lines...

Therefore, if input data is written to the memory in one of the former selection state and the latter selection state, and read from the memory in the other selection state, vertical and horizontal conversion of these data can be performed. .

[Embodiment] FIG. 3 shows the configuration of an embodiment of the present invention. In FIG. 3, 11, 13, 16. and 18 are data registers, 12, 17.19. and 23 are inverters, 14 and 15 are RAMs, 20 and 24 are counters, 22 and 25 are selectors, and 21 is a decoding circuit.

RAMs 14 and 15 have a double buffer configuration, and during one cycle when input data is written to one RAM, the data written in the previous cycle is sent from the other RAM (in a different order than when it was input). ) is read out. A data register is provided on the data input side and data output side of each RAM 14, 15, respectively. For example, in a cycle in which input data is written to one RAM 14, the input side data register 11 of the RAM 14 is is enabled, and the data register 16 on the output side of the RAM 14 is not enabled. Also, at this time, the other RAM 15 is in the cycle of reading data written in the previous cycle data, its input side data register 13 is not enabled, and its output side data register 18 is enabled. The above data registers 11.13, 16. and 18 are
Enabled or disabled by a switching signal.

The addresses supplied to the RAMs 14 and 15 above are:
Counters 20, 24, corresponding to the configuration shown in FIG.
It is generated by a configuration consisting of selectors 22 and 25, inverters 19 and 23, and decoding circuit 21.

Counters 20 and 24 are for outputting the upper 4 bits and lower 4 bits of the above address, respectively, and each has a ripple carry RC output terminal connected to an inverter in order to output a circular address. 1
9 or 23 to its own load control terminal LOAD. As a load input (not shown), the minimum count value of each counter is applied.

Of the two enable terminals ET and EP of the counters 20 and 24, EP is fixed to be enabled at all times, and ET is connected to the outputs of selectors 22 and 25, respectively. The selector 22 receives the always enabled level and the ripple carry output of the counter 24, and selects one of them under control from the decoding circuit 21. Similarly, the selector 25 receives the always enabled level and the ripple carry output of the counter 20, and selects one of them under control from the decoding circuit 21.

When the selector 20 selects the ripple carry output of the counter 24 and the selector 25 selects the constant enable level, the count of the counter 24, which outputs the lower 4 bits of the address in synchronization with a clock (not shown), is cyclical. Each time the count of the counter 24 reaches the maximum value and the ripple carry output becomes valid, the count of the counter 20 that outputs the upper bit of the address is incremented. Thus, in such a selected state, the upper bits of the address are counted up each time the lower bits of the address reach the maximum value. That is,
The address as a whole increases cyclically.

In this way, when the counts of counters 20 and 24 both reach the maximum value, decoding 21
and 25 are switched so that the selector 22 selects the always enabled signal and the selector 25 selects the ripple carry output of the counter 20.

In this switched state, the counter 20 that outputs the upper bits of the address is always enabled, so the count of the counter 20 that outputs the upper bits of the address increases cyclically in synchronization with the above clock.
On the other hand, the count of the counter 24 that outputs the lower bits of the address is incremented each time the count of the counter 20 reaches the maximum value and the ripple carry output becomes valid. In this manner, in such a selection state, the address output from the above configuration changes intermittently by the maximum value of the counter 24 (one output count of the counter 20) every cycle of the clock, and Each time the output of the address reaches the maximum value, the count of the counter 24 that outputs the lower bit of the address is counted and amplified.

Here, in FIG. 4, as mentioned above, the luminance signal 6. i (i=0 to 3), three types of color difference signals Bi,
This shows a digital color image data signal consisting of Ci and Di (i=0 to 3).

These signals are processed in separate filter circuits for the luminance signal and each color difference signal, respectively.
It is required that the data be rearranged as shown in FIG.

Therefore, if the counter 20 in FIG. 3 cyclically outputs hexadecimal numbers CF, and the counter 24 cyclically outputs 0 to 3, then 1. If the count range of the counter 24 is taken as O to 3 on the vertical axis, and the count range of the counter 20 is taken as C-F (hexadecimal) on the horizontal axis, in the former selection state mentioned above, the grid of FIG. Addresses are output in order from the first column to the left of Addresses are output in order from the second row to the second row, and so on.

Therefore, depending on the address output in the former selection state, the input data in FIG. 4 is written to one RAM as shown in FIG. 6, and the address output in the latter selection state is In some cases, the input data of FIG. 4 is written to one of the RAMs as shown in FIG. And in each next cycle,
The data written as shown in FIG. 6 is read by the address output in the latter selection state, and the data written as shown in FIG. 7 is read out in the former selection state. It is read by the address output to. Therefore, in each RAM, vertical and horizontal conversions are performed at the addresses as shown in Figures 2, 6, and 7, and the data input as shown in Figure 4 is read out as shown in Figure 5. It will be done.

In this way, by switching and controlling the enabling timing of the counter that outputs the upper bits of the address and the counter that outputs the lower bits of the address, it is possible to configure a circuit that performs horizontal and vertical conversion of the address without using a ROM or the like.

〔Effect of the invention〕

According to the address translation circuit of the present invention, power consumption is low, the mounting area is small, and it is easy to implement into an LSI.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is an explanatory diagram of memory addresses, Fig. 3 is a configuration diagram of an embodiment of the present invention, and Fig. 4 shows an input data string in an embodiment of the present invention. 5 is a diagram showing an output data string in an embodiment of the present invention, FIG. 6 is a diagram illustrating an example of data written to the memory address in FIG. 2 in an embodiment of the present invention, and FIG. 2 is a diagram showing an example of data written to the memory address in FIG. 2 in the embodiment of the present invention, and FIG. 8 is a configuration diagram of a conventional address conversion circuit. [Explanation of symbols] 1--first counter, 2--second counter, 3--
- first selector, 4... second selector, 5 - decoding/switching means, 11.13, 16.18 - data register, 12.1
7,19.23...-Inverter, 14.15--RA
M, 20.24--counter, 22.25--selector, 21.--decoding circuit. Figure 2D is an explanatory diagram of memory addresses. Figure 6 is a diagram showing an example of data written to the memory address 1 in Figure 2.

Claims (1)

[Claims] In an address translation circuit that generates a write address and a read address for data in a memory, a first counter (1) that generates a cyclical upper address in its enabled state; a second counter (2) that generates a cyclical lower address in an enabled state; a first selector (3) that outputs an enable signal to the first counter (1); 2) a first selector (4) that outputs an enable signal to the first selector (4); decoding/switching means (5) for controlling the selectors (3, 4) of both to switch from one selection to the other selection;
The first selector (3) receives the ripple carry output of the second counter (2) and a constant enable signal at its input terminal, and the second selector (4) receives the ripple carry output of the first counter (1) and the always-enabled signal at its input terminal, and one of the first and second selectors (3, 4) selects the always-enabled signal. and the other selects the ripple carry output of the one selector.