JPH0438568A - Logic simulation processing system between synchronous type ffs - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Logic simulation processing method between synchronous FFs on sending side F
In order to reduce the time required for the delay test between the FF and the receiving FF, a test pattern is supplied to a digital circuit consisting of multiple synchronous FFs built on a simulation device, and Insert a clock with each of the sending FF, receiving FF, and data path between both FFs, which are the test targets, set to a predetermined mode, and check the output change of the receiving FF after inserting this clock. Accordingly, in a logic simulation processing method that performs a delay test between both FFs, the test pattern further includes a logic gate in the clock path of a synchronous FF that is not the subject of the test in such a way that no clock is inserted into the FF. It has a configuration in which the FF is set to a logic state and a clock is inserted only to the FF to be tested.

[Industrial application field]

The present invention relates to a delay test method between a sending side FF (synchronous flip-flop) and a receiving side FF (synchronous flip-flop) in a digital circuit built on a simulation device, and particularly relates to a delay test method for testing a single IC element, large number of ICs
The present invention relates to a delay test method between an arbitrary sending-side FF and a next-stage receiving-side FF in a digital circuit whose unit is an entire printed circuit board on which elements are mounted.

[Conventional technology]

Generally, between a certain sending FF and the next receiving FF in a digital circuit consisting of a plurality of synchronous FFs, logical value data taken into the sending FF by the first clock is transferred to the input terminal of the receiving FF. It is necessary that this logical value data is transmitted to the receiving FF by the next second clock. In order to ensure the above, the delay time required for data transmission from the output side of each sending side FF to the input side of the next stage receiving side FF must be equal to the time interval between the first clock and the second clock. It is necessary that longer overdelay conditions do not occur, and tests are conducted to confirm this. In particular, the scale of logic circuits seen in recent large-scale computers has increased.

With the increase in integration, there is an increasing need to perform this delay test in addition to the conventional function test.

Conventionally, this delay test supplies a test pattern to the digital circuit to set each of the sending FF, the receiving FF, and the data path between both FFs, which are the test targets among the synchronous FFs, into a predetermined mode. Insert a clock in the configured state, and after inserting this clock, the relevant receiving FF
This is done by examining the change in output.

[The problem the question is trying to solve]

Unlike a function test, this type of delay test is a test on the data path of the synchronous FFM being tested, so it is sufficient to insert a clock only into this FF (which is being tested). be. However, in the conventional delay test method, a clock is inserted into all synchronous FFs in a digital circuit, and the delay of logical value data between a certain sending FF and the next receiving FF is sequentially checked. There is. Therefore, the synchronous FF that constitutes the target digital circuit
Because the clock is propagated to all of the test patterns, a large number of unnecessary events occur during simulation during test pattern verification, which increases test time.

Therefore, in the present invention, the test pattern is a conventional sending side FF. In addition to setting each of the receiving FF and the data path between both FFs to a predetermined mode, the logic gate in the clock path of the synchronous FF that is not being tested is set to prevent the clock from being inserted into the FF. The purpose is to reduce the time required to determine the delay between the sending FF and the receiving FF to be tested by setting the logic state to a logical state.

[Means for resolving charges]

FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, reference numeral 1 denotes a sending-side FF to be tested, and logical value data such as input/output thereof is defined by a test pattern 8.

2 is a receiving FF to be tested, and logical value data such as input/output thereof is defined by a test pattern 8.

3 is an FF that is not subject to testing.

4 is a logic gate provided in the (selected) data path between the sending side FFI and the receiving side FF2, and the test pattern 8 activates this path (for example, for a NOR gate, (set the input to “0”).

5.6 is a logic gate provided in each clock path of the FF 1.2 to be tested, and test pattern 8 sets this logic gate to a logic state such that a clock is inserted into the FF concerned. There is.

Reference numeral 7 denotes a logic gate provided in the clock path of the FF 3 that is not subject to the test, and the test pattern 8 sets this logic gate to a logic state such that no clock is inserted into the FF. The test pattern 8 is set so that the clock is not inserted into the FF.

8 is a test pattern, which defines the states of the sending FFI and receiving FF2 that are the test targets, and the data path between both flip-flops, as well as the logic state of the logic gate provided in the clock path of each FF. is set.

Here, test pattern 8 sets the logic state of logic gate 7 so that the clock is not inserted into FF3, and sets the logic state of each logic gate 5, 6 so that the clock does not insert into FF1. It is set to be inserted into FF2. Therefore, the test target FF1. A clock will be inserted only into FF2.

[Effect]

In the present invention, a test pattern that prevents clocks from being inserted into FFs that are not subject to testing is used to simulate the delay determination between the sending FF and the receiving FF, which are the subject of the test. , it is possible to prevent the occurrence of (originally unnecessary) events associated with the insertion of a clock into FFs that are not subject to testing.

〔Example〕

The present invention will be described in detail with reference to FIGS. 2 and 3.

In FIG. 2, 21 to 23 are synchronous FFs in a digital circuit constructed on a simulation device.

Also, the OR game in the clock path of each synchronous FF)29
31 are constructed with clock control dedicated FFs 24 to 26 (of an asynchronous type that is not synchronized with the clock).

Here, in order to determine the delay of logical data in the test path 20 between the sending FF 21 and the receiving FF 22, for example,
The output of the FF is set to be inverted at the first clock.

■The input end initial value and output side initial value of the receiving side FF22,
The output of the FF is set so that it is not inverted by the first clock but is inverted by the second clock.

■Activate the test path 20, that is, the other input terminal 3 of the OR gate 27 and 28 provided in this test path.
2. Set each of 33 to "0".

It is necessary to use test patterns created in this way.

The test pattern in the present invention further includes the test target 0FF21. of these clock control FFs.
The outputs of FFs 24 and 25, which control clock insertion into FF 22, are set to "0", and the output of FF 26, which controls clock insertion to FF 23, which is not subject to testing, is set to "1".

Therefore, when determining the delay of logical data in the test path 20, a clock is inserted only into the sending FF 21 and the receiving FF 22, which correspond to the entrance and exit of this test path.

FIG. 3 shows a simulation processing method in which clocks are inserted only into the sending FF 21 and receiving FF 22 to be tested, without constructing a dedicated clock control FF on the simulation device.

In other words, from among the components of the target digital circuit,
Search for (asynchronous) scan FFs 36 to 38 that can control the other OR gates 29 to 31 in the clock path, and set the outputs of scan FFs 36 and 37 to "0" and the output of scan FF 38 to "1". A locking test pattern is supplied to the digital circuit. This method is effective when it is difficult to add an FF dedicated to clock control due to limitations on the number of gates in a digital circuit.

〔Effect of the invention〕

The present invention provides a clock path for each synchronous FF so that a clock is inserted only into the sending FF and receiving FF that are the test targets among the plurality of synchronous FFs constructed on a simulation device. Since the configuration uses a test pattern that sets the logic state of the logic gate, unnecessary events (due to clock insertion into FFs not subject to test) can be avoided when verifying the delay between synchronous FFs on a simulation device. This does not occur, and the time required for testing can be shortened.

In FIG. 1, 1... Sending side FF to be tested 2... Receiving side FF to be tested 3... FF not to be tested 4... Logic gates 5 in the data path 7.Logic gate in clock path 8..Test pattern

Claims (2)

[Claims] (1) A test pattern is supplied to a digital circuit consisting of multiple synchronous FFs built on a simulation device to test the sending FF, receiving FF, and data path between the two FFs, which are the test targets of the FFs. In a logic simulation processing method that performs a delay test between both FFs by inserting a clock with each FF set to a predetermined mode and checking the output change of the receiving FF after inserting the clock, the test pattern is , Furthermore, the logic gate in the clock path of the synchronous FF that is not the test target is
A logic simulation processing method between synchronous FFs, characterized in that a logic state is set such that no clock is inserted into the F, and a clock is inserted only into the FF that is a test target. (2) The logic simulation processing method between synchronous FFs according to claim 1, wherein the setting of the logic state is performed by an asynchronous FF constructed as a part of the digital circuit.