JPH0439757A - bus controller - Google Patents

Abstract

PURPOSE:To increase the processing speed by transferring the right of using of a bus to other auxiliary processor related to a request, in the case a bus use request state from other auxiliary processor is stored, when the bus occupancy is finished. CONSTITUTION:A storage means A1 of a bus controller A stores a bus use request state from other auxiliary processor Cn which is requested while the auxiliary processor concerned is occupying a bus in each separate auxiliary processor Cn. When the bus occupancy by the auxiliary processor Cn is finished, in the case a bus use request state from other auxiliary processor Cn is stored in the storage means A1, a transfer means A2 does not return the right of using of the bus to a central processor B but transfers it to other auxiliary processor Cn related to the request. In such a way, the right of using of the bus can be transferred directly, and a quick processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control device suitable for quickly performing bus switching in a data processing device.

"Summary of the Invention" This invention, when bus use by one auxiliary processing unit ends, returns the right to use the bus to the central processing unit and then releases it to the other auxiliary processing unit that is waiting for a bus request. The processing speed is increased by eliminating such waste and directly transferring the right to use the bus to another auxiliary processing device that is waiting for the bus request.

[Prior Art] Conventionally, as shown in FIG. The bus control device 5 assigns the right to use the provided address bus AB and data bus DB.
A data processing device that is managed by a computer is known.

In this data processing device, when a bus request signal a (interrupt signal) is input from the auxiliary processing device M2 or the auxiliary processing device 3, the bus control device 5 outputs a bus release request signal S to the MPU 1. . Then, the MPUI releases the address bus AB and data bus DB and outputs a bus release signal C to the bus control device 5. In response to this bus release signal C, the bus control device 5 sends a bus use permission signal d to the auxiliary processing device 2 or 3 related to the bus request.
Output. The auxiliary processing device 2 and the auxiliary processing device 3 that have received this signal perform predetermined processing while exchanging data with the memory 4 using the address bus AB and the data bus DB bus. During this process, the auxiliary processing device 2 or 3 outputs the bus use signal e to the bus control device 5. Then, the bus control device 5
While the bus use signal e is being input, a bus release acknowledgment signal f is output to the MPUI.

Then, while the bus release acknowledgment signal f is being input, M
PU1 is prohibited from using the bus 9 In other words, by stopping the input of the bus release acknowledgment signal f, the bus usage right is
Returned to U1.

Problems to be Solved by the Invention] However, as shown in FIG. 6, if there is a bus request from another auxiliary processing device before one auxiliary processing device finishes processing, the following happens. There was a problem. In addition, in FIG. 6, the numerical value 2.3 attached to the bus request signal a, the bus use permission signal d, and the bus use signal e corresponds to the number 2.3 indicating the auxiliary processing device, respectively. .

That is, while the auxiliary processing device 2 is outputting the bus use signal e2, in other words, before the auxiliary processing device 2 finishes monopolizing the bus, the bus request signal a is output from the auxiliary processing device 3.
3 is output, the bus control device 5 stops outputting the bus release acknowledgment signal f to the MPLII when the auxiliary processing device 2 finishes monopolizing the bus and stops inputting the bus use signal e2, - the right to use the bus is returned to MPU1.

At this time, since the bus release request signal based on the bus request signal a3 from the auxiliary processing device 3 is input from the bus control device 5 to the MPU 1, MP[Jl is the bus release signal C as shown in the figure. is output to the bus control device 5. Therefore, the bus control device 5 outputs a bus use permission signal d3 to the auxiliary processing device 3. Therefore, the auxiliary processing device 3 outputs the bus use signal e3 to the bus control device 5, and starts a predetermined process.Based on this bus use signal e3, the bus control device 5:
A bus release acknowledgment signal f is output to M P L+1.

In this way, conventionally, even when there is an auxiliary processing device waiting for a bus request, the right to use the bus must always be returned to the MPU every time one auxiliary processing device finishes monopolizing the bus. There was an issue with speed.

This is based on the idea that the right to use the bus originally belongs to the MPU and should be released to an auxiliary processing unit as necessary. This is due to the fact that when there is an auxiliary processing device waiting for a bus request to return the right to use the bus, a meaningless return of the right to use the bus is performed.

Therefore, it would be possible to avoid such wasteful return of bus usage rights to the MPU and directly transfer bus usage rights to the next auxiliary processing unit waiting for a bus request, which would improve high-speed processing. It is clear that it is possible.

An object of this invention is to enable the right to use the bus to be transferred directly to another auxiliary processing unit waiting for a bus request, without returning the right to use the bus to the central processing unit, after the exclusive use of the bus by one auxiliary processing unit ends. 9 [Means for Solving the Problems] The means of the present invention are as follows.

A bus control device (see the functional block diagram in Fig. 1; the same applies hereinafter) A has a central processing device B and a plurality of auxiliary processing devices Cn (
n-1, 2, . . . ), and performs bus switching control so that the right to use the bus in each device does not overlap.

The storage means A1 of the bus control device A stores each auxiliary processing device Cn.
Separately, the state of a bus use request from another auxiliary processing device Cn that is requested while the auxiliary processing device Cn is monopolizing the bus is stored.

When the exclusive use of the bus by the auxiliary processing device Cn ends, the transfer means A2 returns the right to use the bus to the central processing unit B, if the storage means A1 stores the state of a bus use request from another auxiliary processing device Cn. Instead, it is transferred to another auxiliary processing device Cn related to the request.

[Work] The operation of the means of this invention is as follows.

For example, now, a bus use permission signal is given from the bus control device A to the auxiliary processing device C1, and while the auxiliary processing device C1 is monopolizing the bus and executing a predetermined process, the auxiliary processing device C2 It is assumed that a bus request signal is input to the bus control device A from the bus controller A.

Then, the storage means A1 of the bus control device A stores, for example, a bus request signal from the auxiliary processing device C2 in correspondence with the auxiliary processing device C1.

Then, for example, when the input of the bus use signal indicating bus exclusive use from the auxiliary processing device C1 stops and it is recognized that the bus exclusive use by the auxiliary processing device C1 has ended, the transfer means A2
The storage means A1 is referred to to search for the presence or absence of a bus use request from another auxiliary processing device Cn. If it is found through this search that there is no bus usage request from another auxiliary processing unit Cn, the transfer means A2 returns the bus usage right to the central processing unit B. C2
Since the transfer means A2 makes a bus use request from the central processing unit B and finds out that it is waiting for the bus, the transfer means A2 does not return the bus use right to the central processing unit B and sends the bus use permission signal to the auxiliary processing unit C2.
The right to use the bus is directly transferred to the auxiliary processing device C2 related to the bus request by outputting the bus to
The right to use the bus can be directly transferred to another auxiliary processing unit waiting for a bus request without returning it to the central processing unit.

[Example] An example will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram of a data processing device, which includes the same MPU 1, multiple auxiliary processing devices 2.3, memory 4, address bus AB, and data bus DB as in the conventional example shown in FIG. ing. Further, although the bus gate 6 is not shown in FIG.
By opening and closing the bus gate 6 based on the MPU
Controls bus release from 1.

Although the bus control device 50 of this embodiment shown in FIG. 2 is slightly different from the conventional bus control device 5, it includes a bus request output circuit 51, a bus use permission signal generation circuit 52, a bus release signal generation circuit 52, and a bus release circuit 52 shown in FIG. The acknowledgment signal generation port B53 itself was also provided in the conventional bus control device 5.

As shown in FIG. 3, the bus control device 50 of this embodiment includes the conventional bus request output circuit 51, bus use permission signal generation circuit 52, and bus release acknowledgment signal generation circuit 53.
Flip-flop FFI, FF2, and gate AND
It has I, AND2, and an OR gate.

The bus request output circuit 51 outputs a signal from the MPU 1 based on the aforementioned bus request signal a2 or a3 from the auxiliary processing device 2 or 3.
A bus release request signal is output to the bus.

The bus use permission signal generation port '7I@52 generates a bus use permission signal d2 or d3 based on the above-mentioned bus release signal C from the MPU 1, and outputs it to the auxiliary processing device 2 or 3. The above-mentioned bus request signal a2 or a3 and bus use signal e2 or e3 are also input to this bus use permission signal generation circuit 52, and the bus request signals a2 and a3 are different from any of the bus use permission signals d2 and d3. It is used to determine whether to generate or output. Furthermore, when the bus use signals e2 and e3 are input, it means that there is an auxiliary processing device 2 or 3 that is monopolizing the bus, so even if the bus release signal C is input, At this point in time, the bus use permission signal d2 or d3 is not generated or outputted, and is used to control so that one device always monopolizes the address bus AB and data bus DB.

That is, when the bus request signal a2 from the auxiliary processing device 2 is input, the bus use permission signal d2 is output to the auxiliary processing device 2, and the bus request signal a3 from the auxiliary processing device 3 is input. , the bus use permission signal d3 is output to the auxiliary processing device 3. Also, for example, the fourth
As shown by the X mark in the figure and FIG. 6, when the bus release signal C is input while the bus use signal e2 is being input, the auxiliary processing device 2 is currently monopolizing the bus. At that point, generation and output of the bus use permission signal d3 to the auxiliary processing device 3 is prohibited.

The bus release acknowledgment signal generation circuit 53 generates the bus release acknowledgment signal f based on the aforementioned bus use signal e2 or C3 from the auxiliary processing device 2 or 3. In addition, in this embodiment, the bus release acknowledgment signal f is corrected as described later and becomes MP
A bus request signal a2 from the auxiliary processing unit 2, a bus release signal C1 from the MPUI, and a bus use signal e3 from the auxiliary processing unit 3 are input to the 9-AND gate AND1 output to the UI, and the output signal causes the flip-flop to be activated. FFI
Set. This flip-flop FF1 is reset by the bus use signal e2 from the auxiliary processing device 2,
The set signal is output to the OR gate OR. Furthermore, the bus request signal a3 from the auxiliary processing unit 3, the bus release signal C1 from the MPUI, and the bus use signal e2 from the auxiliary processing unit 2 are input to the ant gate AND2, and the output signal causes the flip-flop FF2 to be activated. set. This flip-flop FF2 is reset by a bus use signal e3 from the auxiliary processing device 3, and a set signal is output to the OR gate OR.

The above flip-flops FF1 and F are used for the OR gate OR.
In addition to the set signal F2, a bus release acknowledge signal f from the bus release acknowledge signal generation circuit 53 is input. This OR gate OR corrects the bus release acknowledgment signal f based on the set signals from the flip-flops FFI and FF2, and outputs it to the MPU 1 as a bus release acknowledgment correction signal ff, thereby correcting the bus release acknowledgment signal f to the auxiliary processing device 2 related to bus waiting. When .3 exists, it is used to directly transfer the bus usage right released from the MPU 1 to the auxiliary processing device 2.3 that is waiting for the bus, without returning it to the MPLII.

Next, the above-mentioned direct transfer operation of the right to use the bus will be explained with reference to the time chart of FIG.

It is now assumed that the bus release signal C from the MPU 1 is in the state shown in FIG.

In this state, as shown, ant gate AND2
The bus request signal a3, bus release signal C, and bus use signal e2 that are input to Since the signal e2 and the bus release signal C are ゛H parehel, there is a bus request from the auxiliary processing device 3 while the auxiliary processing device 2 is monopolizing the bus, and based on this request, the bus release signal is issued. C is input to the bus control device 50.

In this state, the bus release acknowledgment signal f of °°H°° level is output from the bus release acknowledgment signal generation circuit 853 and is input to the ORKET OR, so the ORKET OR
Bus release acknowledgment correction signal f output from R to MP[Jl
f is also at the H° level. That is, the bus release acknowledgment correction signal ff is at the H° level, and the bus is naturally released from the MPL and il.

Then, as the bus use by the auxiliary processing device 2 is completed, the bus use signal e2 changes to "'L" l/hell,
In response, it is assumed that the bus release acknowledgment signal f from the bus release acknowledgment signal generation circuit 53 also changes to the "L°° level" (see (2)). In this case, if the "L" level bus release acknowledgment signal f is output as is to MPLJl without correction as in the prior art, the right to use the bus will be returned to MPIJ1. However, at this timing in this embodiment, the bus use signal e3 that is reset input to the flip-flop FF2 is "L" and the reset is not activated, so the flip-flop FF2 is set as shown in (3). Since the set signal of flip-flop FF2 is input to the OR gate OR, the bus release acknowledgment correction signal ff output to MPU1 means "signal present" as shown in the figure. In other words, the “L” level portion of the bus release acknowledge signal f is
Since it is interpolated (corrected) by the set signal of FF2 and outputted as the bus release acknowledgment correction signal ff, which remains at the "H" level, the return of the bus usage right (occupancy right) to the MPU 1 is prohibited.

Therefore, as is clear from the comparison between Figures 4 and 6,
The bus use permission signal generation circuit 52 can quickly output the bus use permission signal d3 to the auxiliary processing device 3 to directly transfer the right to use the bus, thereby increasing the overall processing speed. It will be uploaded.

Note that if there is a bus request from the auxiliary processing device 2 while the auxiliary processing device 3 is monopolizing the bus, the flip-flop FFI
performs the same function as the flip-flop FF2 described above.In this way, the purpose is easily achieved by simply adding the flip-flop FFI and the like.

The present invention is not limited to the above-described embodiments, and can be applied, for example, to a case where there are three or more auxiliary processing devices. In this case, flip-flops and AND gates corresponding to the number of auxiliary processing devices are provided, and each ant gate receives a bus release signal from the MPU, a bus request signal from the corresponding auxiliary processing device, and a bus request signal from the corresponding auxiliary processing device. In this case, if bus requests from multiple auxiliary processing units occur while one auxiliary processing unit is monopolizing the bus, their bus exclusive priority order By memorizing this, it is convenient to directly transfer the right to use the bus starting from the auxiliary processing device with the highest priority for bus exclusive use.

It is also possible to perform bus control using software without using flip-flops or the like.

[Effects of the Invention] According to the present invention, after one auxiliary processing device finishes using the bus, the right to use the bus can be directly transferred to another auxiliary processing device waiting for a bus request without returning it to the central processing unit. Rapid processing becomes possible.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of the present invention, FIG. 2 is a block configuration diagram of an embodiment, FIG. 3 is a detailed configuration diagram of the bus control device in FIG. 2, and FIG. 4 is a diagram of bus usage rights in the embodiment. FIG. 5 is a time chart for explaining the direct transfer operation, FIG. 5 is a block diagram of the conventional technique, and FIG. 3 is a time chart for explaining the problems of the conventional technique. 1...MPU, 2.3...Auxiliary processing unit, 50-bus control device, 52--bus use permission signal generation circuit, FFI,
FF2...Flip-flop, AND 1. AND2... Ant gate, OR... Or gate. m4 diagram

Claims (1)

[Claims] Connected between a central processing unit and a plurality of auxiliary processing units,
In a bus control device that performs bus switching control so that bus usage rights do not overlap between devices, each auxiliary processing device can receive requests from other auxiliary processing devices while the auxiliary processing device is monopolizing the bus. A storage means for storing a bus usage request state, and when the auxiliary processing unit finishes monopolizing the bus, if the bus usage request state from another auxiliary processing unit is stored in the storage means, the bus usage right is transferred to the central processing unit. A bus control device comprising: transfer means for transferring the request to another auxiliary processing device without returning it to the device.