JPH043976A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS transistor for a load of a static memory cell constituted by an MIS transistor.

[Summary of the Invention] In a static memory cell used in a semiconductor integrated circuit device, the present invention provides a drive MIS transistor as part of a load MIS transistor formed on the surface of a single crystal silicon substrate with an insulating film interposed therebetween. By using an MIS transistor with the source of the transistor as the gate, it is possible to easily form the source and drain of the load MIS transistor without increasing the manufacturing process, and to reduce the cell size of the static memory cell. 6 [Prior art] A plan view and a cross-sectional view of a static memory cell used in a static RAM realized by the conventional technology are shown in the fourth figure.
and FIG. 5, and its circuit is shown in FIG.

200 is a P-type single crystal silicon substrate, 201.2
02, 203, 204, 205, and 206 are N4 type regions, 207, 208, and 209 are first polycrystalline silicon thin film layers, 210 is a third polycrystalline silicon thin film layer, and 211, 214, and 215 are This is the P4 type region of the third polycrystalline silicon thin film layer, 212 and 213 are the N- type regions of the third polycrystalline silicon thin film layer, and 216 is not under national control in the plan view of Fig. 4. is the aluminum wiring layer.

Reference numerals 220 and 221 are buried contact portions for electrically connecting the N9 type regions 201 and 202 to the first polycrystalline silicon thin film layer 207, respectively, and 222 is an N0 type contact portion.
This is a buried contact portion for electrically connecting the type region 203 and the first polycrystalline silicon thin film layer 208, and 223 is a buried contact portion for electrically connecting the N-type region 204 to the second polycrystalline silicon thin film layer 210. 230 is a contact hole for electrically connecting the first polycrystalline silicon thin film layer 208 and the third polycrystalline silicon thin film layer P'' type region 214. 231 is the second polycrystalline silicon thin film layer 210
and P′″ type region 215 of the third polycrystalline silicon thin film layer.
A contact hole for electrically connecting the
Reference numerals 240 and 241 are contact holes for electrically connecting the N4 type regions 205 and 206 to the aluminum wiring layer, respectively.

In the cross-sectional view of FIG. 5, 250 is a gate insulating film of a transmission N-channel MIS transistor Q3 whose channel is formed on the surface of the P-type single crystal silicon substrate 200;
251 is a gate insulating film of a driving N-channel MIS transistor Q1 whose channel is formed on the surface of the P-type single crystal silicon substrate 200, and 252 is an N-type region of the third polycrystalline silicon thin film layer whose channel is formed on the surface of the single crystal silicon substrate 200. 212 is the gate insulating film of the load P-channel MIS transistor R1, and 253 is the P gate insulating film of the third polycrystalline silicon thin film layer.
This is an interlayer insulating film between the aluminum wiring layer 216 and the N-type regions 211, 214, and 212.

Driving N-channel MIS transistor Q whose channel is formed on the surface of a P-type single crystal silicon base l2ii200
The source train gate of l is 201, 203, 21
0, the source, train, and gate of the driving N-channel MIS transistor Q2 are 202, 204, and 208, and the source or drain of the transmission N-channel MIS transistor Q3 is 2.
03, 205, 209, N-channel MIS for transmission
The source or drain of the transistor Q4 is 204, 206, or 209.

The source, drain, and gate of the load P-channel MIS transistor R1 whose channel is formed in the N-type region 212 of the third polycrystalline silicon thin film layer are 211, 214, and 2.
10, and the source, drain, and gate of the load P-channel MIS transistor R2 formed in the N-type region 213 of the third polycrystalline silicon thin film layer are 211 and 215.
・It is 208.

In the circuit diagram of FIG. 6, the store node S1 is the drain of the driving N-channel MIS transistor Q1, the source or drain 203 of the transmission N-channel MIS transistor QB, or the drain 214 of the load P-channel MIS transistor R1. . The long door node S2 is connected to the drain of the drive N-channel MIS transistor Q2, the source or drain 204 of the transmission N-channel MIS transistor Q4, or the load P-channel MIS transistor.
This is the drain 215 of transistor R2. Word line W
L is 209 of the -th polycrystalline silicon thin film layer.

VSS is the first polycrystalline silicon thin film layer 207 provided parallel to the word line WL209. VDD is
A third layer of polycrystalline silicon is parallel to the word line WL209, is provided on the first polycrystalline Zinocon thin film layer 207 of the VSS, and is integrally formed with the sources of the load P-channel M/S transistors R1 and R2. There is a P-type region 211 of the thin film layer. The bit line pair BL/BL is an aluminum wiring layer provided perpendicular to the word line WL209, but is omitted in the plan view of FIG. 4, and the aluminum wiring layer 216 of the bit line BL is omitted in the cross-sectional view of FIG. The country has national authority only.

[Problems to be Solved by the Invention] By the way, when designing a static memory cell in which the channel is provided on an insulating film, the channel length of the load MIS transistor must be determined by the diffusion of impurities through the gate insulating film. Since the source and drain are formed in a polycrystalline silicon thin film layer having a large coefficient, the channel must be set longer than the channel length of the M/S transistor provided on the surface of the semiconductor substrate.

However, in the prior art described above, N-channel MIS transistors Q1 and Q2 for driving static memory cells
A joint gate structure is used in which the gate of the load P-channel MIS transistor R1 and the gate of the load P-channel MIS transistor R2 are shared, and the load P-channel MIS transistor R
Since the sources and drains of transistors Q1 and R2 are formed after the gate is formed, the channel length of the driving N-channel M/S transistors Q1 and Q2 is determined by the joint gate a-
If we tried to make the dimensions the same as those of the N-channel MIS transistors that do not use a structure, there would be no room for the gates and sources of the load P-channel MIS transistors R1 and R2, and the gates and drains of the drive N-channel MIS transistors.
It is not possible to make the channel lengths of IS transistors Ql and Q2 the same as that of N-channel MIS transistors that do not use a joint gate structure.
There is a problem that the formation area of the S transistors Q1 and Q2 cannot be minimized.

The present invention is intended to solve these problems, and its purpose is to reduce the channel length of the driving N-channel MIS transistors Ql and Q2 without increasing the manufacturing process and without using a joint gate structure. The object of the present invention is to provide a structure of load P-channel MISh transistors R1 and R2 that can be made to have the same dimensions as M/S transistors.

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention includes driving MIS transistors Q1 and Q2 whose channels are formed on the surface of a semiconductor substrate and a transmission MIS transistor Q.
A static memory cell is constituted by the load MIS transistors R1 and R2 whose channels are formed in a semiconductor thin film layer on an insulating film.
Some of the transistors R1 and R2 drive the gates of MI.
It is characterized in that it is an MIS transistor with the source of the S transistor Q1 or Q2.

Static transmission is achieved by driving M-S transistors Q1 and Q2 whose channels are formed on the surface of the semiconductor substrate, transmission MIS transistors Q3 and Q4 whose channels are formed in a semiconductor thin film layer on an insulating film, and load MIS transistors R1 and R2. The type memory cell is configured and the load M
A part of transistors R1 and -R2 drives the gate M
MIS used as the source of IS transistor Q1 or Q2
It is characterized by being a transistor.

[Example] As an example of the present invention, a CMIS static type memory cell diagram and a cross-sectional view are shown in FIGS. 1 and 2, and a CMIS static type memory cell diagram shown in FIG. Shown in Figure 2.

100 is a P-type single crystal silicon substrate, 101.1
02, 103, 104, 105, 106 are N type regions, 107, 108, 109 are the first polycrystalline silicon thin film layer, 110 is the second polycrystalline silicon thin film layer, 111, 114・115 is a P type region of the third polycrystalline silicon thin film layer, 112 and 113 are N- type regions of the third polycrystalline silicon thin film layer, and 11
Reference numeral 6 indicates an aluminum wiring layer, which is not designated by the government in the plan view of FIG.

13C1131 is a buried contact portion for electrically connecting the N′″ type regions 101 and 102 to the −th layer polycrystalline silicon thin film layer 107, and 132 is an N
Type 4 region 103 and first polycrystalline silicon thin film layer 108
133 is a buried contact portion for electrically connecting the N-type region 104 with the second polycrystalline silicon thin film layer 110; 140 is a buried contact portion for electrically connecting the A contact hole 141 is for electrically connecting the first polycrystalline silicon thin film layer 108 and the P'' type region 114 of the third polycrystalline silicon thin film layer. layer 11
P type region 11 of the 0 and 3rd polycrystalline silicon thin film layers
5 is a contact hole for electrically connecting
Reference numerals 150 and 151 are contact holes for electrically connecting the N'' type regions 105 and 106 to the aluminum wiring layer, respectively.

In the cross-sectional view of FIG. 2, 160 is a gate insulating film of a transmission N-channel MIS transistor Q3 whose channel is formed on the surface of the P-type single crystal silicon substrate 100;
Reference numeral 161 denotes a gate insulating film of a driving N-channel MISh transistor Ql whose channel is formed on the surface of the P-type single crystal silicon substrate 100, and reference numeral 162 denotes an N-type region of the third polycrystalline silicon thin film layer whose channel is formed on the surface of the single crystal silicon substrate 100. P-channel M of the load P-channel MIS transistor formed in 112
IS) Gate insulating film of transistor R11, 163
164 is the gate insulating film of the P-channel MIS transistor R12 of the load P-channel MIS transistor whose channel is formed in the N-type region 112 of the third polycrystalline silicon thin film layer; This is an interlayer insulating film between the P' and N- type regions 111, 114 and 112 of the crystalline silicon thin film layer and the aluminum wiring layer 116.

The source, drain, and gate of the driving N-channel MIS transistor Q1, whose channel is formed on the surface of the P-type single crystal silicon substrate 100, are composed of the N'' type region 101 - the N'' type region 103 and the second layer of polycrystalline silicon. The source, drain, and gate of the driving N-channel MIS transistor Q2 are formed by a film 110, and the source, drain, and gate of the driving N-channel MIS transistor Q2 are formed in an N-type region @102, an N-type region @104,
-th polycrystalline silicon layer 108, which is the source or drain layer of the transmission N-channel MISh transistor Q3.
The drain or source gate is an N-type region 103N.
The source, drain train, or source gate of the transmission N-channel MIS transistor Q4 is the polycrystalline dinocon layer 109 of the 105th layer of the 105th layer of the N2 type region. This is a polycrystalline silicon layer 109.

Channel is N-type head of third layer of polycrystalline silicon thin film layer @
The source, drain, and gate of the P-channel M-type S transistor for load, which is formed by connecting P-channel M-type S transistors R11 and R12 in series, which are formed in the P-channel M-type S transistor 112 and do not form a P-type region in the middle, are connected to the P-channel M-type S transistor. Third layer P゛ type polycrystalline silicon layer 111 which is the source of transistor R12/P channel MIS transistor R11
The third P゛゛polycrystalline silicon layer 11 which is the drain of
4. This is the second polycrystalline silicon layer 110 which is the gate of the P-channel MIS transistor R11. The source of the P-channel MIS transistor for load is formed in the N-type region 113 of the third polycrystalline silicon thin film layer, and is configured by the series connection of P-channel MIS transistors R21 and R22 with no P-type region formed in the middle. The drain and gate are P-channel MIS transistor R2
The third P0 type polycrystalline silicon layer 11 which is the source of No. 2
1-P-type polycrystalline Zinocon layer 115, which is the train of the P-channel MIS transistor R21, and the first polycrystalline Zinocon layer 108, which is the gate of the P-channel MIS transistor R21.

In the circuit diagram of FIG. 3, word line WL is layer 109 of the polycrystalline silicon thin film layer. VSS is a first polycrystalline silicon thin film layer 107 provided in parallel with the word line WL109, and is connected to the sources of the driving N-channel MIS transistors Q1 and Q2. VDD
is parallel to the word line WL109, is provided on the first polycrystalline silicon thin film layer 107 connected to vSS, and is formed integrally with the sources of P-channel MIS transistors R12 and R22 of the P-channel MIS transistor for load. This is a P-shaped head 111 of the third polycrystalline silicon thin film layer. The store node Sl is the drain of the drive N-channel MIS transistor Q1 and the transmission N
Source or drain 103 of channel MIS transistor Q3 or drain 11 of P-channel MIS transistor R11 of P-channel MIS transistor for load
It is 4. Store node S2 is a driving N-channel MI
Drain of S transistor Q2 and N channel M for transmission
This is the source or drain 104 of the mechanical S transistor Q4 or the drain 115 of the P-channel MISI transistor R21 of the load P-channel MIS transistor. P-channel MI of drive N-channel MIS transistors Ql and Q2 and load P-channel MIS transistor
The gates of S transistors R11 and R21 are connected to store nodes Sl and S2, respectively. P for load
The sources of the P-channel MIS transistors R11 and R21 of the P-channel MIS transistors for the load are N''' type regions 101 and 102 whose gates are connected to VSS.
This is the channel of IS transistors R12 and R22.

The word line WL is the 10th layer of the -th polycrystalline silicon thin film layer.
It is 9. VSS is the first polycrystalline silicon thin film layer 107 provided parallel to the word line WL109.

VDD is parallel to the word line WL109, is provided on the first polycrystalline silicon thin film layer 107 connected to VSS, and is integrated with the sources of P-channel MIS transistors R12 and R22 of the load P-channel MIS transistors. There is a P° type region 111 of the third polycrystalline silicon thin film layer formed. The bit line pair BL/BL is provided orthogonally to the word line WL109, and is connected to the N-type slopes 05 and 106, which are the drains or sources of the transmission MISI transistors Q3 and Q4, through contact holes 150 and 151. Although the connected aluminum wiring layer is omitted in the plan view of FIG. 1, only the aluminum wiring layer 116, which is designated as bit line B in the cross-sectional view of FIG. 2, is under national control.

According to the configuration of the P-channel MIS transistor for load of the present invention, the P-channel MIS transistor for CMIS static type memory cell
As part of the channel MIS transistor, the gate is
By using P-channel MIS transistors R12 and R22 as N'' type regions connected to S, the sources of P-channel MIS transistors R11 and R21 can be used as the channels of P-channel MIS transistors R12 and R22. The distance between the P゛ type regions or the loading P which is the high impurity concentration of the third polycrystalline silicon thin film layer
The spacing 111 and 114 or 111 and 115 between the source and drain of the channel MISI transistor can be widened regardless of the channel length of the driving N-channel MIS transistors Q1 and Q2.

In addition, the present invention provides a polycide thin film layer in place of the -th and second polycrystalline silicon thin film layers, and a P' type and N-type polycrystalline silicon thin film layer in place of the third layer P' type and N- type polycrystalline silicon thin film layers. The semiconductor material used is not limited, such as a - type single crystal silicon thin film layer or a channel only N- type single crystal silicon or polycrystalline silicon thin film layer. In addition, an N-channel M in which transmission MIS transistors Q3 and Q4 are formed via an insulating film.
Needless to say, similar effects can be obtained as an IS transistor.

[Effects of the Invention] As described above, by using an N''' type tilted wall connected to the SS of a part of the gate as a P-channel MIS transistor for a CMIS static type memory cell, an N-channel MIS for driving can be realized. Since the channel length of the transistor can be minimized, the area occupied by the driving N-channel MIS transistor can be reduced, and the chip size and manufacturing cost can be significantly reduced.

[Brief explanation of the drawing]

1 and 2 are a plan view and a sectional view according to the present invention. FIG. 3 shows the CM according to the present invention shown in FIGS. 1 and 2.
FIG. 2 is a diagram of an IS static type memory cell. 4 and 5 are a plan view and a sectional view according to the prior art. FIG. 6 shows the C according to the prior art shown in FIGS. 4 and 5.
FIG. 2 is a diagram of a MIS static type memory cell. 101, 102, 103, 104, 105.106...
・N-type regions 07, 108, 109 ... -th layer polycrystalline silicon layer 110 ... second layer polycrystalline silicon layer 111, 114
．． 115...Third layer P゛゛polycrystalline silicon layer 112.113...Third layer N-type polycrystalline silicon layer and above Applicant Seiko Epson Corporation Agent Patent attorney Kizobe Suzuki (and 1 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1) Driving MI in which a channel is formed on the surface of a semiconductor substrate
A static memory cell is constituted by S transistors Q1 and Q2, transmission MIS transistors Q3 and Q4, and load MIS transistors R1 and R2 whose channels are formed in a semiconductor thin film layer on an insulating film.
MI where part of the IS transistors R1 and R2 uses the gate as the source of the driving MIS transistor Q1 or Q2
A semiconductor integrated circuit device characterized by being an S transistor. 2) Driving MI with a channel formed on the surface of the semiconductor substrate
A transmission MIS transistor Q3 in which S transistors Q1 and Q2 and a channel are formed in a semiconductor thin film layer on an insulating film.
and Q4 and the load MIS transistors R1 and R2 constitute a static type memory cell.
MI where part of the IS transistors R1 and R2 uses the gate as the source of the driving MIS transistor Q1 or Q2
A semiconductor integrated circuit device characterized by being an S transistor. 3) The drive MIS transistor Q1 or Q2 and the transmission MIS transistor Q3 or Q4 according to claim 1 or 2 are MIS transistors of a first conductivity type, and the load MIS transistors R1 and R2 are of the first conductivity type. A semiconductor integrated circuit device comprising MIS transistors of a different second conductivity type. 4) A semiconductor integrated circuit device according to claim 3, wherein the first conductivity type is N type and the second conductivity type is P type. 5) The driving MIS transistor Q1 or Q2 according to claim 2 is a first conductivity type MIS transistor, and the transmission MIS transistor Q3 or Q4 and the load MIS transistors R1 and R2 are of a first conductivity type. A semiconductor integrated circuit device characterized by being a two-conductivity type MIS transistor. 6) A semiconductor integrated circuit device according to claim 5, wherein the first conductivity type is N type and the second conductivity type is P type. 7) A semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor substrate is a single crystal silicon substrate and the semiconductor thin film layer is a polycrystalline silicon thin film layer.