JPH0439933B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a synchronization detection circuit used in digital transmission systems such as backbone transmission systems, public transmission systems, and subscriber systems.

(Prior Art) Transmission technology using optical fibers as a transmission medium has made remarkable progress, and it is becoming possible to transmit information at a rate of several hundred Mbps to several Gbps. In order to effectively use a digital transmission system with a large capacity, time division multiplexing can be considered, but since high-speed processing is required, it is necessary to make the frame configuration as simple as possible, and to downsize and simplify the circuit. There used to be. One such method is a bit-based time division multiplexing method, and FIG. 3 is a frame configuration diagram of a general bit multiplexing method. In the figure, one frame consists of K bits, one frame is divided into K channels in bit units, and one channel is assigned to the frame channel, F is the frame channel, and #1 to #K-1 are the frame channels. There are K-1 channels in bits. In this method, when bit multiplexing, a unique frame pattern is inserted one bit at a time into frame channel F in units of several frames, and in synchronization detection, data is separated in units of channels and then separated from any channel. Synchronization is detected by detecting a frame channel depending on whether the signal sequence matches the inserted unique frame pattern.

Another method is to divide the frame into subframes and distribute the frame pattern to each subframe. FIG. 4 shows a general example of the frame structure. In the figure, one frame is divided into L subframes, each subframe is I bit unit, and one frame (I×L) is divided into L subframes.
It has a bit structure, and one frame pattern is sequentially inserted into the first bit of each subframe. Fi (i=1, 2..., L) is a frame bit inserted into the first bit of each subframe, and #1 to #L indicate subframes in units of I bits. In this method (F ₁ F ₂ F ₃ …
...F _L-1 F _L ) is the frame pattern, and in synchronization detection, the frame pattern consisting of (F ₁ F ₂ F ₃ ...F _L-1 F _L ) is detected from the separated signal string. Synchronous detection is performed by It is not necessary to insert the frame pattern into all of the frame bits F ₁ to F _L ; for example, if the frame pattern is inserted into the frame bits F ₁ F ₃ F ₅ ..., the remaining frame bits F ₂ F ₄ F ₆ …
It is also possible to transmit information such as a transmission path monitor or a service monitor using...

(Problems to be Solved by the Invention) In the bit multiplexing system as shown in FIG.
One of the bits is used. In order to downsize and simplify the circuit, the length of K that constitutes one frame cannot be made too large, so the signal amount of the frame pattern is as large as 1/K in the amount of transmitted data. . This overhead is expected to increase as the transmission capacity increases and speed increases, and when considering system reliability and serviceability, channels for transmitting information such as transmission path monitors and service monitors are also required. This trend will increase significantly. In addition, in the method shown in Fig. 4, in which the frame is divided into subframes and the frame pattern is distributed to each subframe, there is a unique frame pattern (F ₁ F ₂ F ₃ ...F _{L -1F L} )
Synchronization is detected by detecting a signal string that matches from the separated signal strings, and frame synchronization and subframe synchronization are ensured. By inserting and transmitting information such as a transmission path monitor or service monitor in the frame bits _F1 to _FL , or by increasing the number of subframes L in one frame and the number I of subframe constituent bits, the circuit can be improved. Information transmission with less overhead relative to the amount of transmitted data is possible without increasing complexity.

However, once synchronization is lost, in order to detect a signal sequence that matches the frame pattern (F ₁ F ₂ F ₃ ...F _L-1 F _L ) from the separated signal sequence, Since hunting between one frame is required, the worst synchronization period required until synchronization is restored is L x I x 1 frame [SEC], which depends on the number of subframes L and the number of subframe constituent bits I.
If this becomes large, the average time required to detect a frame pattern (F ₁ F ₂ F ₃ . . . F _L-1 F _L ) after once synchronization is lost increases.
The present invention solves these problems by reducing the overhead of the amount of frame pattern signals relative to the amount of transmitted data without increasing the circuit scale or complexity, making it easy to detect frame patterns, and reducing the average time required to recover synchronization. An object of the present invention is to provide a synchronization detection circuit suitable for a high-speed, large-capacity transmission system that can reduce time.

(Means for Solving the Problem) The present invention uses one bit of the M bits for frame synchronization in a frame that is divided into N subframes and each subframe has an M bit configuration, As a frame synchronization pattern, a cyclic code consisting of one word and N bits is generated from a generator polynomial, and an expansion circuit extracts the received signal every M bits, and an expansion circuit connected to the output of the expansion circuit extracts the received signal from the data string. Synchronization detection is performed using means for calculating the remainder between a code polynomial whose coefficients are N bits and the generator polynomial.

(Function) When performing synchronization detection, it is desirable to downsize and simplify the circuit, by dividing the frame structure on the transmission path into subframes and dispersing the frame pattern into the first bit of each subframe. In the insertion and synchronization detection, it is possible to detect the frame pattern, that is, synchronization detection, by extracting the frame bits inserted in the first bit of each subframe, which reduces the operating speed required of the synchronization detection circuit. This makes it possible to construct a synchronization detection circuit suitable for high-speed, large-capacity transmission systems by reducing the circuit size and simplifying the circuit. This increase is expected to realize a transmission system that reduces the overhead of the frame pattern signal amount relative to the amount of transmitted data.Furthermore, the frame pattern inserted into the first bit of each subframe can be generated from an arbitrary generator polynomial. Since it is a cyclic code consisting of 1 word and N bits, in synchronization detection, the strong properties of the cyclic code are used to combine it with a code polynomial whose coefficients are 1 word and N bits extracted from one series of separated signals. Frame patterns can be easily detected by calculating the division remainder.
Subframe synchronization can be ensured. At the same time, by searching the N bits of one word, which are the coefficients of the code polynomial, it is possible to detect where the beginning of a subframe is, so frame synchronization can be quickly ensured, and once an out-of-synchronization state occurs, It is expected that the average time required to return to a synchronized state will be shortened. At this time, it is not necessarily necessary to search all N bits of one word; it is possible to detect one word of information by searching for a bit length shorter than that, which reduces the size and complexity of the synchronization detection circuit. It is also possible to further reduce the amount.
Furthermore, by arbitrarily selecting the generator polynomial and code length N, it is possible to increase the minimum Hamming distance d between the generated cyclic codes. By using this property, it is possible to reduce bit errors in the frame pattern. It is possible to realize a synchronization detection circuit that is robust against

(Example) A synchronization detection circuit of the present invention will be described below.

FIG. 1 is a diagram showing a frame structure in the present invention. In the figure, one frame is divided into seven subframes, each subframe is composed of M bits, and one frame is composed of (7 x M) bits, and the first 1 bit of each subframe is sequentially divided into frames. The pattern is inserted one bit at a time. Fi (i=1, 2, . . . 7) is a frame bit inserted into the leading bit of each subframe, and #1 to #7 indicate subframes in units of M bits. The frame pattern is, for example, (F ₁ F ₂ F ₃ F ₄ F ₅ F ₆ F ₇ ) = (1100010) ... (1), and the code word is generally (a ₀ a ₁ a ₂ ... a _{o -1} ), then a ₀ is n-1st, a ₁ is n-2nd, a _o-1 is 0
Next, by corresponding, the code polynomial F(x) is written as F(x)=a _o-1 +a _o-2 X+a _o-3 X ² +… +a ₁ X ^n-2 +aoX ^n-1 ……(2) can be expressed. Here, it is assumed that the code length is n, and in terms of time, a high-order term a ₀ appears first, progresses sequentially to lower-order terms, and finally a _o-1 is mentioned.

As can be seen from equation (2), when the code word is made up of a 7-bit string, the code polynomial F(x) can be expressed as a polynomial of degree 6, and equation (1) becomes F(x) =X+X ⁵ +X ⁶ ...(3) If the generator polynomial G(x) is G(x)=1+X+X ³ ...(4) then F(x)=Q(x)G(x)... If a polynomial Q(x) that satisfies (5) exists, the polynomial in equation (3) has been generated from the generator polynomial in equation (4). The polynomial Q(x) that satisfies this is Q(x)=X+X ² +X ³ (6) and is a polynomial whose coefficient is the input bit string (1110).

From the above, it can be seen that the frame pattern (1100010) is a code generated from the generator polynomial in equation (4). Furthermore, as shown in the publication ``Coding Logic'' (Hiroshi Miyagawa, Yoshihiro Iwadare, Hideki Imai, P Shokodo, 194-197), in a field modulo 2, generally the code length is set to n. When the generator polynomial G(x) is X ⁿ⁺¹
The code word generated from G(x) when dividing G(x) forms a cyclic code. Therefore, the generating polynomial of equation (4) is (X ⁷ +1)/G(x)=(X ⁷ +1)/(X ³ +X+1)=X
⁴ +X ² +X+1 ...(7) Then, divide X ⁷ +1 by X ⁴ +X ² +X+1, so
The codeword of code length 7 generated from the generator polynomial in equation (4) becomes a cyclic code. That is, W = 1100010 1000101 0001011 0010110 0101100 1011000 0110001 (8) Each row element of matrix F in equation (8) generates a cyclic code with code length 7, W ₁ = (1100010) (9-1) W ₂ = ( 1000101) (9-2) W ₃ = (0001011) (9-3) W ₄ = (0010110) (9-4) W ₅ = (0101100) (9-5) W ₆ = (1011000) (9-6 ) W ₇ = (0110001) (9-7) When W ₁ , W ₂ , . . . , W ₇ are coefficients, the code polynomial is divisible by the generator polynomial in equation (4). Furthermore, the minimum Hamming distance d of the cyclic code is uniquely determined by the selection of the generator polynomial and code length, and when the code length is 7 and equation (4) is used as the generator polynomial, the minimum Hamming distance is d d = 3 (10) ( The relationship between the Hamming length, generator polynomial, and code length is described in references P249 to P254 of the previous term.

FIG. 2 shows an embodiment of the synchronization detection circuit of the present invention, which detects synchronization from the frame shown in FIG. In the figure, 201 is an information and information input terminal (S _IN ), 202 is a serial/parallel converter (S-P), 203 ₁ is a clock line, 203
₂ is a clock control signal line, 204 ₁ to 204 _M are M parallel-converted information lines and information output terminals, 2
05 is the clock control circuit (CLK CTT), 206
is a heptad counter, 207 is a control gate, 208 ₁
~208 ₂ is the MOD2 adder, 209 ₁ ~209 ₃
is a delay element with a length of one subframe. In the same figure, an information input terminal 201 having the frame structure shown in FIG.
₁ to _204M , and the information line ₂₀₄₁ , which is one series of the parallelized information lines, becomes an input signal to the clock control circuit 205 and the adder ₂₀₈₁ of MOD2. On the other hand, the MOD2 adder 208 ₁ ~
208 ₂ and one subframe length delay element 209 ₁
~209 ₃ is the generator polynomial G(x)=1+X+X ³ of equation (4)
This constitutes a divider.

In addition, a clock signal of f ₀ /7 [Hz] when the transmission line is f ₀ is serially connected to the heptad counter 206.
It is sent from the parallel converter 202, and using this output, the delay elements 209 ₁ to 209 are sent at one frame interval.
The contents of 209 ₃ have been cleared. As a result, the divider sequentially divides the information line 2 in each frame period.
₀₄₁ is used to divide the polynomial that uses the 7 bits transmitted as a code word of 1 word by the generating polynomial of equation (4), and the remainder is divided by the delay element 209.
₁ to 209 ₃ . This corresponds to successively dividing the generator polynomial of equation (4) by the code polynomial whose code word is a bit string extracted from each of the seven subframes, and the remainder is That is, the delay elements 209 ₁ to 2 after the division is completed.
If the values of ₀₉₃ are all zero, the signal sent from the information line ₂₀₄₁ is a frame pattern distributed and allocated to the first bit of each subframe, and one delay element ₂₀₉₁ to ₂₀₉₃ is sent. However, if it is non-zero, it means that the signal sent from the information line ₂₀₄₁ is not a frame pattern.
In this way, frame patterns can be easily detected. Possible case 1 where the remainder becomes zero
The frame pattern of 1 word, 7 bits sent during the frame period is expressed by formulas (9-1) (9-2)...
...(9-7), and the fact that the remainder is zero means that subframe synchronization is ensured. If the remainder is not zero, synchronization cannot be detected. This means that the system has fallen into an asynchronous state, and synchronization detection is performed after the state has fallen into an asynchronous state. In other words, until subframe synchronization is ensured, at worst, hunting only needs to be done by the subframe length M. The synchronization recovery time in the worst case is M x 1 frame [SEC] After securing subframe synchronization, search the 1 word 7 bits sent from the information line 204 ₁ during 1 frame to ensure frame synchronization. do it. In this search, it is not necessary to search all the 7 bits of one word, and as can be seen from equations (9-1), (9-2), ..., (9-7), at least By searching only 3 bits, you can confirm that they are mutually exclusive, and you can immediately detect which frame pattern is used to ensure subframe synchronization. This information can be used to ensure subframe synchronization. After that, it can be done immediately and easily.
The inputs of the control gate 207 are the delay elements 209 ₁ to 2
This is a gate that detects whether the division remainder is zero or non-zero using the output of ₀₉₃ , and the output becomes an input to the clock control circuit 205. Furthermore, the input of the clock control circuit 205 includes an information line 204 and the output of a hexadecimal counter 206, and this clock control circuit has at least a 3-bit memory and a 1-bit memory.
Of the frame pattern of 1 word and 7 bits sent between frames, information on the first 3 bits is held, and this information and the output of the control gate 207 are used to confirm that subframe synchronization is secured and to use both frames. Control information for ensuring synchronization is sent to the serial/parallel converter 2 using the clock control signal line 203 ₂ .
02 and frame synchronization is ensured.

The above description has been given using an example in which the number of subframes in one frame is 7, the generator polynomial is 1+X+X ³ , and the cyclic code is (1100010). However, the present invention is not limited to these combinations, and can be applied to various combinations. Various combinations are possible. Furthermore, it is not necessary to insert each bit of the frame pattern in correspondence with the first bit of each subframe. For example, it is not necessary to insert the bits of the frame pattern in correspondence with each other in every other subframe, and the remaining bits are inserted into the transmission path. It can also be used for information transmission such as a monitoring monitor or a service monitor.

(Effects of the Invention) As described above, if the synchronization detection circuit according to the present invention is used, the amount of overhead of the signal amount of the frame pattern relative to the amount of transmitted data, the ease of synchronization detection, and the average asynchronous duration characteristics can be improved compared to the synchronization detection with the conventional configuration. It can be seen that this is a significant improvement compared to the circuit.

This invention is a synchronization detection circuit suitable for such high-speed, large-capacity transmission systems, and will enable even higher speeds and
It is expected that it will be used in transmission systems that are increasing in capacity.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a frame configuration according to the present invention, FIG. 2 is a diagram showing an example of the configuration of a synchronization detection circuit according to the present invention, and FIGS. 3 and 4 are diagrams showing conventional frame configurations. In the figure, 201 is an input information and information input terminal;
02 is a serial/parallel converter, 203 ₁ is a clock line,
203 ₂ is a clock control signal line, 204 ₁ to 204
_M is M parallel-converted information lines and information output terminals, 205 is a clock control circuit, 206 is a hexadecimal counter, 207 is a control gate, 208 ₁ to 208 ₂
is an adder of MOD2, and 209 ₁ to 209 ₃ are delay elements of one time slot.

Claims (1)

[Claims] 1 In a frame that is divided into N subframes and each subframe has an M bit configuration, one bit of the M bits is used for frame synchronization, and a frame synchronization pattern is generated from a generator polynomial. an expansion circuit that extracts the received signal every M bits using a cyclic code consisting of 1 word and N bits; A frame synchronization detection circuit comprising means for calculating a remainder with a generator polynomial.