JPH0440864B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a MOS semiconductor device including a substrate voltage generation circuit.

2. Description of the Related Art The potential of a semiconductor substrate on which a large number of semiconductor elements are formed is maintained at a predetermined value to ensure stable operation of the semiconductor elements. The potential can be applied externally, but this requires terminal pins, so integrated circuits often incorporate a substrate voltage generation circuit. A typical example of such a substrate voltage generating circuit is shown in FIG. 1a.
In this figure, 10 is an oscillator, 12 is a waveform shaping circuit (inverter), 14 is a pumping circuit, V _CC is a positive power supply voltage, V _SS is a ground level of the power supply, and V _BB is a substrate voltage. Q ₁ , Q ₂ , Q ₄ , Q ₅ , Q ₇ , Q ₈ , Q ₁₀ ,
_Q11 is a MOS transistor, and _Q9 is a MOS capacitor. H (high) and L generated by the oscillator 10
When a rectangular wave signal that changes to (low) level and its inverted signal obtained by applying it to the inverter 12 are applied to the transistors Q ₇ and Q ₈ of the pumping circuit 14,
These are turned on and off alternately. now transistor
When Q ₇ is on and Q ₈ is off, the potential at node N ₁ is MOS
The capacitor Q ₉ 's capacitive coupling raises the voltage toward V _CC , but the clamping transistor Q ₁₀ turns on and
The potential of the node _N1 is held near the threshold voltage Vth of the clamping transistor _Q10 . In this state, transistor _Q7 is turned off and _Q8 is turned on.
The gate voltage of MOS capacitor _Q9 transitions from H level to L level. At this time, the node _N1 becomes more negative in potential than the substrate potential due to capacitive coupling, causing the diode-connected transistor _Q11 to conduct, thereby drawing out the charge from the substrate.

FIG. 1b shows the voltage variation at node _N1 . In this way, by alternately turning on and off transistors Q ₇ and Q ₈ , the charge on the substrate is released to the ground terminal V _SS via the pumping capacitor Q ₉ , and the substrate potential is set to a predetermined negative value. This is the function of the voltage generation circuit. Figure 2 shows the above transistor
The structure of Q ₁₁ , MOS capacitor Q ₉ and terminal Ta is shown, and 16 is a semiconductor substrate which is p-type in this example. 18 and 20 are N ⁺ type diffusion layers and transistors
It becomes the source, drain, etc. of _Q11 . 1 is a wiring that connects the terminal Ta to the substrate 16.

Since such a substrate voltage generation circuit is built into the substrate and is fixed, it is inconvenient in V _BB margin tests and the like. That is, FIG. 3 is a V _CC vs. V _BB characteristic diagram showing the range of the power supply voltage V _CC and substrate voltage V _BB in which the semiconductor device can normally operate.
V _CC1 and V _CC2 indicate the upper and lower limits of the standard voltage. It is expected that a semiconductor circuit made using a defect-free manufacturing process will have an operable area within the solid line _C2 , but a semiconductor circuit with some defects will have a
In many cases, the operating range is only indicated by C ₃ . Such abnormal margins must be discovered and excluded during wafer probing tests. In order to discover abnormal margins, try operating at points _P1 , _P2, etc. within the _C2 frame and outside the _C3 frame, but as mentioned above, if the board voltage generation circuit is built-in, The potential cannot be changed arbitrarily. That is, the output voltage of the substrate voltage generating circuit is related to the power supply voltage and has a characteristic as shown by the straight line _C4 in FIG. Therefore P ₁ ,
An operating point such as P ₂ cannot be obtained.

If the substrate voltage is forcibly changed by applying an external potential to the terminal Ta, the following problem will occur. That is, if the potential of the terminal Ta is made shallow by an external voltage in order to obtain an operating point such as the current point P ₁ , the substrate voltage generation circuit itself is still operating, so in this case the potential of the node N ₁ becomes V _BB becomes larger and more negative. This is the PN created by node _N1 together with the substrate as shown in Figure 2.
The junction becomes forward biased and a large forward current flows, injecting a large amount of electrons into the substrate 16 from node _N1 . These electrons may enter the channel of the MOS transistor, interfering with the normal operation of the semiconductor device, and making it impossible to detect elements with abnormal V _CC -V _BB margin characteristics.

The present invention aims to improve these points.
The feature is that a substrate voltage generation circuit having an oscillator and a pumping circuit that operates in response to the output signal of the oscillator and applies a substrate potential to the semiconductor substrate via a diode-connected transistor is mounted on the same semiconductor substrate. A method for testing a built-in semiconductor device, the semiconductor circuit being built into the semiconductor substrate, comprising the steps of: putting the substrate voltage generation circuit in a dormant state; and forcing the substrate potential to change using an external power source. and performing a substrate potential margin test by operating the method.
Next, this will be explained in detail with reference to the drawings.

4a and 4b show a semiconductor device to which the test method of the present invention can be applied, and the same parts as in FIG. 1 are given the same reference numerals. Q ₁₂ , Q ₁₃ , Q ₁₄ are MOS transistors, and the output of the oscillator 10 is from these transistors.
Added to Q ₁₃ gate. The gate of transistor _Q14 is connected to the power supply V _CC through impedance element R.
It is also connected directly to the test probe terminal PD. Since the terminal PD is used only during the wafer probing test, there is no need to use the terminal pin of the integrated circuit, and it can simply be placed on the board as a pad.

An integrated circuit equipped with such a substrate voltage generation circuit is
The operation is no different from the conventional one. That is, the transistor _Q14 is on because its gate is pulled up to the power supply V _CC by the impedance element R, and the H and L outputs of the oscillator 10 turn on and off the transistor _Q13 , and the inverted output of the oscillator 10 is output from the output terminal _N2. A signal is generated. This is applied to the gate of the transistor Q ₈ of the pumping circuit 14 and also to the transistor Q ₂ of the inverter 12, and the inverted output of the inverter is applied to the gate of the transistor Q 8 of the pumping circuit.
Join the gate of Q ₇ . Therefore, these transistors Q ₇ and Q ₈ repeatedly turn on and off in reverse to each other,
Perform the pumping operation described above.

During the test, transistor _Q14 is turned off by applying a grounded probe to terminal PD. In this way, the oscillator output is not added to the pumping circuit, and the pumping circuit 14 becomes inactive. In such a state, a voltage is applied to the terminal Ta by an external power supply to obtain the operating states such as the points P ₁ and P ₂ described above, and it is possible to check whether there is a margin abnormality.
When the measurement is completed, the probe is removed from the terminal PD, and the substrate voltage generation circuit returns to normal operation.

As explained above, according to the present invention, the V _CC -V _BB margin of a semiconductor device equipped with a substrate voltage generation circuit can be tested by a simple means, and it is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the substrate voltage generation circuit, Fig. 2 is a schematic sectional view showing the actual structure of a part of it, Fig. 3 is a V _CC -V _BB margin characteristic diagram, and Fig. 4 is a test of the present invention. FIG. 2 is a circuit diagram showing a semiconductor device to which the method can be applied. In the drawing, 10 is an oscillator, 14 is a pumping circuit,
_Q14 is a control MOS transistor, R is a resistor, V _CC
is the power supply, and PD and Ta are the terminals.

Claims (1)

[Claims] 1. A substrate voltage generation circuit having an oscillator and a pumping circuit that operates in response to an output signal of the oscillator and applies a substrate potential to the semiconductor substrate via a diode-connected transistor is provided on the same semiconductor substrate. A method for testing a semiconductor device built on a semiconductor substrate, the method comprising: placing the substrate voltage generation circuit in a dormant state; and forcibly changing the substrate potential using an external power source. 1. A method for testing a semiconductor device, comprising the step of performing a substrate potential margin test by operating a semiconductor circuit.