JPH0440913B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for sampling analog information signals, such as television signals.

As will be explained in more detail below, in the present invention, the video information signal is sampled at a rate that is a multiple of the subcarrier frequency, such that a large number of samples are taken during each subcarrier cycle. In an embodiment, the apparatus controlled by the sampling clock samples the video information signal at a rate of three times the subcarrier (SC) frequency, with three samples being taken during each cycle of the SC ( (at phase positions of 0°, 120°, and 240°). For color video information signals, the phase of the sample with respect to the SC determines the hue of the video image during playback, so sampling the information signal at a position other than the correct phase will result in degraded playback. .

The invention ensures that samples are taken precisely at the phase positions necessary for the color signal to be accurately reproduced during playback. The apparatus of the invention is arranged in close enough proximity to the preferred sample locations (in the preferred embodiment, approximately 0°, 120°, and 240° each of the preferred sample locations)
Use a phase lock loop to provide sampling (within 20°). At this time, the actual sample is examined to determine whether a phase error really exists, and the sample is accurately 0°, 120°,
The sampling clock is adjusted so that it is taken at a 240° phase position. As a result, if an error occurs due to temperature drift, etc., this can be effectively compensated for.

It is therefore an object of the invention to provide a device for reliably sampling an information signal having an associated carrier signal, such that the sampling occurs at a precise phase position with respect to the carrier signal. .

It is an object of the present invention to test an actual sample to determine whether an error exists between the actual and desired phase position of the sample, so as to substantially eliminate such error. The object of the present invention is to provide a sampling device of the above-mentioned type which adjusts the sampling to the desired level.

More broadly with respect to FIGS. 1-3, the present invention relates to a recording and reproducing apparatus 70, indicated at 70 in FIG.
It has two racks 71 and 72 containing various monitoring and control elements, particularly shown on the top of rack 72, along with the electrical circuitry associated with the device 70. The device 70 also includes:
There is a pair of disk drives 73 located adjacent to the right rack 72, each drive having a disk pack 75 attached thereto. Although two disk drives are shown in FIG. 1, additional disk drives may be added to increase the on-line storage capacity of device 70. A single disk drive can also be used, but a single disk drive alone cannot perform many of the functions described below. The operation of the device 70 is
It is controlled by one or more operators using a number of access station devices, such as the internal access station 78 in the remote access station or rack 72 shown. If desired, a video monitor 79, vector and "A" oscilloscope may be used as shown on rack 72. A "phase" control switch 81 is located above the internal access station 78.

The example device includes an internal access station 78
or controlled by an operator using a remote access station 76. Both stations have a keyboard, which has numeric and function keys and bars, and a 32-character display 82, which in use provides a readout of the information necessary to perform the functional operations, as well as an address display. Displays information regarding the identity of a certain still being displayed and other information. The remote access station 76 shown in FIG. 2 is representative of each remote access station, and in a preferred embodiment, up to seven remote access stations may be used to control device 70. The internal access station keyboard, shown generally as 83 in FIG. 1 and also shown in enlarged cutaway view in FIG. 3, has greater operating capacity than the remote access station (which has fewer function keys). . As will be discussed below, the keyboard includes a large set of keys generally shown at 84 and a smaller set of keys 85 shown on the left side of the keyboard. A control switch 86 may also be provided to toggle between normal and erase operations to avoid the possibility of inadvertent erasure of stills currently in use.

In the highly simplified block diagram shown in FIG.
receives a video input signal which is then processed by a recording signal interface circuit 89.
and from there all disk drives 73
A signal is given to A gating circuit in the selected disk drive 73 causes the signal to be recorded in the selected drive. More than one disk drive 73 can also be selected at the same time to record the video signal provided by recording signal interface circuit 89. A switch circuit can be used in place of the signal interface and associated gate circuits, supplying the signal provided by the recording signal processing circuit 88 only to the selected disk drive whose disk pack 75 is to record the signal. You may also do so.
During playback, the signal from one of the disk drives is applied to a playback switch circuit 90 which provides a signal to one of the playback channels 91, each of which provides a video output channel. A computer control system 92 is interfaced with a recording signal processing circuit 88, a recording signal interface circuit 89, a playback switch circuit 90, and a disk drive 73 to control the overall operation of the various elements of the embodiment apparatus, and is remotely accessible. station 76
and an internal access station 78 . As will be explained below, if a disk pack is online, i.e. it is connected to disk drive 7.
3, the operator can select a particular disk for still recording. In this regard, the embodiment device is adapted to identify up to 64 separate disk packs, only one of which can be arbitrarily placed on one disk drive. It should be understood that it addresses the disk pack rather than the disk pack. Therefore, if the embodiment device has two disk drives, only two disk packs can be used in one drive.
You can be forced to go online at any time. The operator can use the access station keyboard 83 to enter the address of one disk pack on which he wishes to record stills, and by computer interaction with the disk drive loaded with the selected disk pack, the selected online disk Recording operations can be performed on packs. Similarly, the operator can play still frames from a disk pack of one disk drive and can define the playback channel in which he wishes to play the still frames.

The embodiment device has four main modes of operation: (1) record/erase, (2) playback, (3) sequence assembly, and 4) sequence playback. Recording and playback operations will first be described with reference to FIGS. 6 and 7. These figures each show a schematic block diagram of the recording and reproducing signal paths associated with one of the disk drives 73.

In the recording signal path block diagram of FIG. 6, the composite video input signal is first applied to an input stage circuit 93, where the signal is clamped and the synchronization and subcarrier components are separated from the composite video signal. taken out. The input stage circuitry also regenerates the sync and subcarrier signals for use during subsequent playback, and thus the regenerated sync and subcarrier signals serve as reference signals used in operation by the subsequent elements. is applied to a clock generator 94 which generates a clock signal. The clamped analog video signal with the color burst component is then provided to an analog-to-digital (A/D) converter 95, which
Gives an output signal at a sampling rate of 10.7MHz. In this case, each sample value consists of 8 bits of information. The output digital video signal is a non-return to zero (NRZ) code. That is, the binary code defines "1" as a high level and "0" as an equivalent low level. The digitized video signal is produced in eight parallel lines (each line corresponding to a respective bit) and then applied to an encoder and sync word inserter 96, where the digital magnetic For recording, it is converted into a special recording code (mirror code or mirror squared code) which is particularly good. This circuit also inserts synchronization words into alternate television lines for a particular phase angle of the color subcarrier represented by the color burst synchronization component. This synchronization word is used as a reference for correction of time base and skew errors that occur during playback between the eight parallel bits of data that must be combined to define the numerical value represented by each sample. The digital video information in eight parallel lines is then transferred to a recording amplifier circuit 153 and a selected disk drive 73 which switches between two groups of eight recording heads for recording the digitized video signal by disk drive 73. and associated head switch circuit 9
7 is given. The disk drive is servo-controlled so that the rotational speed of its spindle is locked in vertical synchronization and the speed of the rotating disk is 3600 revolutions per minute. By locking the spindle drive to vertical synchronization, the device
One television field is recorded per revolution, and eight data streams are recorded on eight disk surfaces simultaneously. When recording of one field is completed, the recording amplifier circuit 153 and the head switch circuit 97
The second of the television frames is recorded on another set of eight disk surfaces so that an image frame, two scanned television fields, are recorded in two revolutions of the disk drive using 16 heads. Another set of heads is commanded to record the fields simultaneously. Each disk pack located in one disk drive preferably contains 815 cylinders, each having 19 sides and thus recording 815 digital television frames. There is one read/write head for each of the 19 recording surfaces of a disk pack, and all heads are mounted in vertical alignment on a common carriage whose position is controlled by a linear motor. There is. It should be understood that one cylinder is defined to have all recording surfaces located on the same radius of one disk pack. However, the term ``track'' is used in the text instead of ``cylinder,'' and thus track is meant to include all recording surfaces of the same radius, ie, the entire surface on the cylinder. Thus, an addressed track for recording or reproducing stills actually points to the 19 individual surfaces on the cylinder that can be used in that radius. available for recording
One of the 19 surfaces is used for recording addresses and other reference information in place of active video information and is specifically referred to as the "data track." Two of the 19 surfaces are utilized to record one variation bit, and 16 surfaces are used to record video data as further described below. Also, one of the heads, commonly referred to as the servo head, moves over the 20th disk pack surface, which contains only servo track information previously recorded by the pack manufacturer. This servo track has two functions:
Following a search command, the head stack traverses the servo tracks that are counted to determine the immediate position of the head, and after completion of the search mode, the servo head linearly moves the head carriage to center and hold the head carriage on the appropriate servo track. Generates an error signal used to control motor position.
Using such a feedpack system, it is possible to achieve a radial packing density of approximately 400 tracks per inch, or a total of 815 tracks per diskpack.

Because the device does not record analog video signals due to frequency response limitations of disk pack memory, the video signals are digitized for recording. Because a digitized signal is recorded, the system's video signal-to-noise ratio is determined primarily by quantization noise rather than recording medium and preamplifier noise, as in conventional video tape recorders. In this way, the device has approximately
It produces a signal-to-noise ratio of 58 dB, effects such as moiré and residual time base errors are absent, and digital random errors in the storage channel are low enough to cause incidental transmission errors that are often virtually invisible. It is.

By recording digital data streams on each of the eight disk sides at a rate of 10.7 megabits per second, the linear packing density of the device is approximately 6000 bits per inch, which is much higher than traditional disk drive applications in data processing. Approximately 60% larger than that used for.

During playback, in FIG. 7, the head reads or plays back digital video information from eight sides per field to obtain a recorded channel-encoded digital video signal from the two fields forming each image frame. . The reproduced signal is
amplifying a data stream of digital video information carried by eight data bit lines and providing it to an equalization and data detection circuit 99;
The signal is applied to a regenerative amplifier circuit 155 and a head switch circuit 97 associated with the selected disk driver 73. The equalization circuit compensates for the phase and amplitude distortions introduced into the signal by the band-limiting effects of the recording and playback processes, ensuring that the zero-crossings of the playback signal are clearly and accurately located. Following the equalization action,
The channel encoded signal on each data bit line is processed as described below for transmission on twisted pair lines to the regeneration circuitry of the signal system. The channel encoded signal to be processed is in the form of a pulse for each zero crossing or signal state transition of the channel encoded signal. Twisted pair lines for the eight data bits of digital video information provide processed channel encoded signals to the decoder and time base correction circuit 100 of one or more playback channels 91 of the apparatus. The decoder and time base correction circuit 100 reprocesses the received signals, puts them into a channel encoded format, decodes the signals into non-zero return digital form, and time base corrects the digital signals with respect to the station reference. ,
Eliminates time displacement errors (commonly referred to as skew errors) and timing distortions between data bit lines in each data stream carried by the data bit lines. To facilitate reproduction signal processing, a phase continuous clock signal is used to cause the decoder and time base correction circuit 100 and subsequent circuits to operate at appropriate times. As will be discussed in more detail below, this allows the time base corrector portion of circuit 100 to accurately determine the synchronization word during alternate playback of image frames. The time base corrector portion of circuit 100 thus serves to align the eight bits defining one sample and remove timing distortion in each data bit line relative to the station reference. However, the above-mentioned error in the position of the synchronization word causes the image to shift in the horizontal direction during alternate playback, resulting in the appearance of jitter in the displayed video. Each playback channel has a decoder/time axis correction circuit 10.
It should be noted that within each playback channel, each of the eight data bit streams passes through a separate decoder and time base correction circuit. The output of circuit 100 is then applied to a comb filter and chroma inverter circuit 101 which separates the chroma or chroma information, which also has a four-field
Selectively invert and recombine the signals for reconstruction of the NTSC sequence. This reconstructed digital signal is fed to a circuit 127 that adjusts for errors in the position of the synchronization word in the alternating playback of two recorded fields of video information, and the adjusted video signal provides an analog video signal. A digital to analog converter 102 is provided. The new synchronization and burst are then applied to process amplifier 103.
are summed to produce the composite video analog output signal of the desired playback channel 91.

Details of the video signal system shown in FIGS. 5 and 6 are shown in FIGS. 7A and 7B. However, the previously used reference numbers remain where the corresponding functions are performed. 7th A
The block diagrams of Figures 7B and 7B also illustrate the flow of video data through the signaling system, along with other interconnecting lines necessary to control the timing and synchronization of the circuits represented by the various blocks. Contains lines. Also shown is the interconnection of the signal system to the computer control system 92, in this case the seventh
The input and output lines from the various blocks in FIGS. A and 7B are lines that extend to computer control system 92.

In addition, the embodiment device has 525 horizontal synchronization pulses (also referred to as "H synchronization" in the text) generated at a rate of about 15.734 Hz, which means that the period between consecutive H pulses is about 63.5 microseconds. Has a television field consisting of lines of books
It shall be described regarding use in the NTSC system. Furthermore, vertical blanking in the NTSC system occurs at a frequency of 60 Hz, ie the chrominance information is modulated on a subcarrier signal having a frequency of approximately 3.58 megahertz (MHz). Because of the phase relationship of the color subcarrier with respect to the horizontal synchronization signal, the NTSC color signal has four field sequences, commonly referred to as color frames. The subcarrier frequency of 3.58Hz is 1
×Subcarrier frequency is simply denoted SC, and similarly the clocking frequencies used include 1/2SC, 3SC and 6SO. This 3x subcarrier frequency (3SC) arises because a sampling rate of 3x subcarrier frequency, ie 10.7 MHz, is used during sampling of the analog composite video signal for digitization of the signal. NTSC composite video signals are generally known.

With reference to FIG. 7A, before discussing the function of each block shown in the figure, a broad general idea regarding the overall operation of the illustrated signal system should be understood. First, video input circuit 93A
The video input signal sent to is an analog signal provided to an analog-to-digital converter 95 for processing. The output of the converter contains video information in digital format, and the digitized data is further processed and recorded on a disk pack in digital format. Similarly, this data is recovered from a disk pack, time-corrected, chroma-separated, processed using digital techniques, and then converted to analog by a digital-to-analog converter 102.
and sync burst insertion circuit 103 provides a composite video output.

In the analog-to-digital converter 95,
The analog composite video signal is sampled at a sampling rate of three times the nominal subcarrier cycle, or 3SC (10.7MHz), and each sample is digitally quantized into an 8-bit digital word.
A sampling clock having a frequency that is three times the NTSC subcarrier frequency or any odd multiple is necessarily an odd multiple of half the horizontal line frequency.
If such a sampling clock is phase continuous between each line, its phase at the beginning of successive lines will change. The use of such a line-to-line phase continuous sampling clock results in the instantaneous amplitude of the analog signal being sampled between successive lines a different number of times with respect to the beginning of successive lines. Therefore, the quantized samples are not line-to-line vertically aligned. Vertical alignment of line-to-line samples combines the separate chroma components of the television signal by combining quantized samples from three consecutive (all odd or even fields) television lines of the television field. is required to facilitate the use of a digital comb filter to obtain (chromaticity), where the three television lines are T (top), M (middle), and B (bottom). C=M-1/2(T+B) (luminance) Y=M+1/2(T+B) It is expressed as follows.

If the samples of the NTSC television signal are even multiples of the subcarrier frequency, then the comb filter technique is ideal. This is because the phase of the sampling clock does not change from line to line. Thus, the digital code word or quantized sample represents the instantaneous amplitude of each line of the analog signal at the same point in time relative to the start of each line, and all of the samples in three consecutive lines are distributed from top to middle to bottom. It is vertically aligned towards the line.

It is clear from Figure 7C(1) that there is no vertical alignment of consecutive line samples when using a 3SC line-to-line phase continuous sampling clock. The cycle of the subcarrier of television line 1 is shown, sampled at the positive transitions of the 3SC sample clock (Figure 7C(3)), where upward transitions have arrows representing "X" sample points. , which is placed on the subcarrier of television line 1 at every sample point.
As shown, there are three samples in each cycle of the subcarrier. However, during television line 2, the next following line, the subcarriers have opposite phases as shown in FIG. ) with respect to the subcarrier of television line 2 (Fig. 7C(4)), so that during television line 2 the sample is on the upward transition
(2) Go to the position indicated by the × in the figure), and line 1
〜2× samples are shifted by 60°, therefore,
This adversely affects the response of the comb filter, which uses the instantaneous amplitude of the analog signal in the above formula to obtain the correct chromaticity information. Therefore, samples taken on all odd lines are vertically aligned, and samples taken on all even lines are vertically aligned, but samples taken on even lines are vertically aligned. for the sample on the line
It is clear that it is displaced by 60°.

To avoid problems caused by sampling at odd multiples of the subcarrier frequency, i.e. 3SC in the device described in the text, vertical alignment on all lines can be achieved by changing the phase of the sampling clock for alternate lines. . FIG. 7C(5) shows the television line 2 whose phase is reversed with respect to the sampling phase for the television line 2 shown in FIG. 7C(4).
3SC sampling clock is shown. Sampling of the upward transition at the "0" sampling point results in samples designated by "0" on the subcarrier for line 2, as shown in FIG. 7C(2). Therefore, television line 1
The subcarrier sample points (“×”) for
With respect to the sample point ('0') sampled using the sampling clock of every other phase as shown in Figure 7C(5) than that which normally occurs as shown in Figure 9C(4). Vertically aligned. This technique is commonly referred to as Phase Alternating Line Encoding or PALE, and the term “PALE
Words such as "made", "DALE", etc. are used in the description of the device described in the text.

Although the device described here uses a comb filter technique with a 3SC or 10.7 MHz sampling rate and requires the use of a PALE sampling clock, the use of a 4SC sampling frequency eliminates the need for PALE processing. You will find that it does. The use of 4SC sampling frequency is
If the frequency response of the recording medium, ie, the disk pack of the disk drive device, is sufficient to allow operation at a frequency of 4SC, 14.3 MHz, it is within the scope of the concept of the device described in this text. in this case,
It will be appreciated that standard disk drives used for data processing applications operate primarily in the range of about 6 1/2 megabits, and recording at speeds of 10.7 MHz represents a significant improvement in the pack density of the disk pack itself. .

Another important aspect of the operation of the apparatus, which is a result of the use of PALE processing, is also described above with respect to FIG. 7C. Changes in the phase of the sampling clock on each successive line necessitate phase discontinuities with respect to the SC. During channel encoding of the signal for use in later recording, it is further advantageous to channel encode the digitally quantized samples with respect to a continuous phase clock, so that there is no line-to-line phase discontinuity. be. For this reason, during recording, the PALE'd data present at the output of the analog-to-digital converter 95 is clocked out from the channel encoder 96 using a clock with a phase of 3 SC that is continuous (i.e., unbroken) from line to line. . However, clocking the encoder 96 using a continuous phase clock from line to line will shift the data in time on alternate lines by 1/2 cycle of 3SCs, so sampling using the PALE clock will This would compromise the resulting line-to-line sample time alignment. During playback, the chroma or saturation processing circuitry requires samples of the data to be vertically aligned line by line (this is why the PALE sample clock was first used in analog-to-digital converters 95). ,
It is necessary to retime or reclock the data from the continuous phase clock to the PALE clock to remove sample time disturbances and allow the saturation comb filter to process the data without error. Briefly, A/D converter 95 samples the analog signal using a PALE clock with line-by-line phase discontinuity. For recording, channel encoder 96 is connected to the PALE clock for use by the saturation processing circuit.
Retiming the NRZ information during playback and after decoding encodes the required PALE data using a line-by-line continuous phase clock. However, retiming from a phase-continuous clock to a PALE clock is not possible during a transfer mode of operation when video data recorded on one disk drive memory is transferred to another disk drive memory for recording and playback. Not implemented. In such a case,
Line-by-line continuous phase data clocking of the reproduced video data is preserved and data is re-recorded without disturbing the data clocking.

The above consideration applies to lines 1 and 2.
PALE data will now be described with respect to FIG. 7C as shown in FIGS. 7C(6) and 7C(7), respectively. Bits A1 to E1 are shown in Figure 9C.
(1) A series of bit cells representing instantaneous samples of the analog video signal occurring on line 1 corresponding to the x shown in the figure, each bit cell being the seventh bit cell.
C(3) Sustains the full clock cycle of the 3SC clock shown in the diagram. Similarly, bit cells A2 through E2 on line 2 are obtained by sampling at ``0'' in Figure 7C(2) using the PALE sample clock shown in Figure 7C(5) for television line 2. Indicates the data that will be displayed. Since the PALE data is clocked with a continuous phase 3SC clock per line, the arrows below the bit cells shown in Figures 7C(6) and 7C(7) are The clocking points of the bit cell are shown shifted to the relationship shown in FIG. The start of each bit cell occurs at this clocking point, and the cell levels are continuous over the bit cell interval so that the bit cells maintain their coincidence during clocking.

Data from continuous phase clock line by line
Retime the PALE clock to vertically align the bit cell (sample) so that A2 is equal to A1 and B2 is
In order to achieve vertical alignment such as B1..., the retiming from the continuous phase clock to the PALE clock must be done correctly, otherwise misalignment of the bit cells will occur. In this regard, the retiming or reclocking must be complementary, i.e. bit cells that are clocked in their proper part in serial reclocking from PALE
Reclocking must be clocked to the left to cause proper playback. Therefore, given the line-by-line continuous phase clocked data shown in Figures 7C(8) and 7C(9), the solid arrows indicate the correct complementary clocking for the two television lines. , resulting in the retiming of the data into a PALE clock with vertically aligned A1 and A2 bits as shown in FIGS. 7C(10) and 7C(11). Bit cells clocked to the right from reclocking from PALE to continuous,
Note that any bit cell (eg, A1) with an associated clocking arrow in FIGS. 7C(6) and 7C(8) is clocked to the left with the opposite transformation state. . If complementary clocking is not implemented, the bits are clocked in Figures 7C(12) and 7C(1).
3) Section 7C(8) such that it yields the relationship shown in the figure.
It is not properly aligned as shown by the dotted clocking arrows in Figure 7C(9).
Reclocking from PALE to continuation or vice versa can occur at various locations as will become apparent from the description below.

Additionally, an NTSC television signal has no specification or definition between the horizontal (H) synchronization pulse that occurs on each line and the phase angle of the subcarrier signal, except that the phase of the subcarrier varies by 180° from line to line. It will also be clear that there is no relationship. In other words, the phase angle of the subcarrier signal with respect to the H synchronization signal will change if the video signal source changes.
This variation makes the H sync signal undesirable for use for device control. Therefore, according to the invention, we use the subcarrier of the input signal represented by the color burst synchronization component as the basic timing reference for the system, and instead of the H synchronization of the signal we use the new H synchronization used for timing.
Specifies synchronization related signals. This new H sync related signal is selected to be at half the frequency of the nominal horizontal line. The reason is that this displays the total number of cycles of the subcarrier frequency (455), ie two complete horizontal lines of the subcarrier frequency. Furthermore, the H synchronization related signals are given a special relationship to the subcarriers, ie they are synchronized with respect to the phase angle of the subcarriers. In the recording portion of the signal system, a sync word is inserted into the video signal on alternate television lines at locations approximately corresponding to the H sync locations of the video signal, which correspond to the color burst carrier of the video signal. It is phase coherent with respect to a particular phase angle of the SC resulting from the synchronous component. The location of the new H synchronization related signal is defined at the beginning of each image frame,
A video signal is provided having an H sync related signal maintained for the duration of an image frame and accurately and consistently defined with respect to the phase of the subcarriers of the video signal. For the regeneration part of the signal system, an H synchronization related signal, denoted H/2, is provided, which corresponds to a specific phase angle of the reference input subcarrier, the phase angle of which is selectable by the phase control of the regeneration system. is respecified so that it is coherent with respect to

This redefined H synchronization related signal H/2 is used as the basic timing reference signal of the system during playback operations.

Recording of the system using the redefined H synchronization related signals as the horizontal synchronization reference for the system,
Processing signals for playback and other operations is facilitated because a consistent time relationship exists between the subcarriers of the video signal and the redefined H-sync related signals.

Additionally, the use of time-varying internal horizontal reference signals and subcarrier reference signals with respect to the reference synchronization of the television station ensures that the television signal reaches the remote location at the appropriate point in time after undergoing the normal propagation delays that occur. It becomes possible to do so.

Again in the block diagrams of FIGS. 7A and 7B, the analog video signal is applied to the input side of an input circuit 93A which performs some operations during processing of the analog video signal before it is applied to an analog to digital converter 95. . Input circuit 9
3A is included in the video signal for use in amplifying the analog video signal, performing DC restoration, and generating timing signals for the signaling system.
Separate the Sync component, detect the level of the HSync chip, and then clip the chip level.
Additionally, HSync is isolated using precision Sync circuitry used in generating regenerated Sync. This circuit also produces a regenerated SC signal derived from the H/2 reference signal generated from the burst of the video input, or from the video input HSync in the absence of a burst.

Video input circuit 93 shown at the bottom left of FIG. 9A.
A and the reference input circuit 93B have similar functions, that is,
It serves primarily as a video input circuit for the signal recording part of the signal system and as a reference input circuit mainly for the reproduction part of the signal system. Therefore, the same circuit is used for manufacturing and service convenience. However, the input circuits are connected within the device to receive only the input signals needed to perform their respective functions, and although the same signals are produced in each circuit, not all of them are used in each circuit. The reference input to the reference input circuit is the station reference color black video signal containing all components of a color television signal except that its active video portion is at the black level. Thus, bursts, HSync, etc. are present in reference input circuit 93B when they are in video input circuit 93A. In addition, the reference input circuit 93B uses an H phase position adjustment circuit that includes an operator-operated phase control switch 81 to adjust the H phase position of the regenerated HSync used in the regeneration section of the signal system. Receives the H position control signal from a knob switch such as.

As shown, many of the output signals provided by input circuits 93A and 93B are provided to reference logic circuits 125A and 125B associated with each input circuit. Reference logic circuit 125A during recording operation mode
uses inputs from video input circuit 93A, analog-to-digital converter 95, and computer control system 92 to generate multiple recording clock and PALE flag signals at frequencies of 6SC and 1/2SC through precision phase-lock loop circuits. .
PALE flag and 3SC signal are reference logic circuit 125
A is used by A to produce a 3SC PALE sampling clock signal whose phase is set for each line of the video signal by the PALE flag at a frequency of H/2. The PALE flag signal changes state at the rate described above, although the two states of the PALE flag signal are unequal in time, ie, the two states of the PALE flag signal are unequal in time. This is done asymmetrically so that the sampling clock phase for the color burst portion of the video signal coincides with the phase of the subcarrier, and then only that portion of the television line has a sampling phase that alternates on successive lines. This PALE clock is coupled to an analog-to-digital converter 95 and the 3SC
That is, it is a sampling clock signal for obtaining samples at 10.7MHz.

The reference logic circuit 125B is the reference input circuit 93B.
and computer control system 92 to generate a clock reference signal and various other timing control signals at the frequency of the SC. These signals are used in operating the device in modes other than the input video signal recording mode.

During record and playback modes of operation, the reference logic also provides servo Sync for each disk drive to properly operate the disk drives in the proper phase.
Generate a signal.

During the playback mode and other modes of operation other than recording the input video signal, the reference clock generator 98 provides the clock generator 98 with different timings required by the various clocks and parts of the signal system used in such modes. Generate control signals. The reference clock generator includes a reference input circuit 93B,
Reference logic 125B, signal system regeneration section,
Using operator control switch input,
It generates clock signals at frequencies of 6SC, 3SC, SC and 1/2SC as well as various other timing control signals. Reference logic circuits 125A, 125B and reference clock generator circuit 98 both have a signal system clock generator 94 that provides system timing control signals.

Clamped HSync from video input board
The striped analog video signal is applied to an analog-to-digital converter 95 that converts the signal to an 8-bit binary encoded signal in a PALE-processed NRZ (non-returning) format that is applied to an encoder switch 126. This analog-to-digital converter 95 is structurally and functionally the same as that built in the Digital Swim Base Collector No. TBC-800 manufactured by Ampecs, and therefore will not be shown in detail in this text. A diagram of the analog-to-digital converter 95 is shown in catalog No. 7896382-02 published October 1975. The specific circuit of the analog-to-digital converter is shown in schematic diagram No. 3-31/32 of the catalog.
1374256, and schematic diagram No. 1374259 on pages 3-37/38 of the same catalog. These and other schematic diagrams are cited in the text for reference.

The output from the analog-to-digital converter is then sent to an encoder switch 126 which receives data from the converter or from the data transfer circuit 129.
The switching circuit typically receives 8-bit digitized video data from a computer. As described below, data transfer circuit 129 allows video information to be transferred from one disk drive to another, as previously described with respect to operation of the device using remote or internal access stations. . In the transfer mode of operation, digitized information is read from the disk drive and
It is decoded to NRZ digital format, timebase corrected, and then provided to an encoder switch that can select any source of digitized video information for encoder 96. Because the channel encoded data recorded on disk drive 73 was clocked with a continuous phase clock, the NRZ data received by data transfer circuit 129 is also timed with respect to the continuous phase clock. Normally, the data transfer circuit 129 is
to the PALE clock signal so that the data provided to the chroma separator and processing circuit 101 is in the proper PALE processed format.
Provided with a PALE flag signal used to perform retiming of NRZ digital data.
During the transfer mode of operation, this retiming is not necessary. Encoder switch 126 includes circuitry that interrupts the coupling of the PALE flag signal to data transfer circuit 129, thereby preventing retiming of the NRZ data with respect to the PALE clock during the data transfer mode.

Encoder switch 126 is controlled by computer control system 92 and gates video data from either the input video or transfer path. This switch also toggles between video and reference 6SC and 1/2SC timing signals since the reference timing signal is used during data transfer mode and the video timing signal is used during record mode. The encoder switch also controls the TV image so that it is visible that the still location or address for the still is unoccupied and therefore available for recording and for providing signals to perform diagnostic functions. It is also used to generate a signal that produces a blanking cross. With respect to the sync word inserter, encoder switch 126 combines the 8-bit digital video signal from the analog-to-digital converter and the timing signal sent to encoder 96 from the timing reference.

The 8-bit data from encoder switch 126 is then applied to encoder 96, which first generates a variation bit and then converts it into a mirror square channel code form, which is a self-clocking, DC-less, non-recurring type of code. Encode the data that has been PALE-processed to the mat.

While the PLAE processed data is provided to the encoder, the output of the encoder is a 9-bit data stream with phase continuity for 3SCs (if integrity is included). Data clocked with continuous phases is easier to process, especially during decoding operations. DC-free codes can occur because one logical state predominates for a period of time that can have the effect of perturbing the data in the playback process.
Avoid DC components.

In controlled band information that does not carry DC, the binary waveform is subject to distortions at zero crossing locations that cannot be removed by linear response compensation circuits. Such distortion, commonly referred to as baseline wander, acts to reduce the effective signal-to-noise ratio, modify the zero crossings of the signal, and thus degrade the bit reliability of the decoded signal. The common transmission format or channel data code used in recording and reproducing systems was established on October 22, 1963.
Miller U.S. Pat. In Miller's code, a logical 1 is represented by a signal conversion at a particular location, ie, the mid cell, and a logical 0 is represented by a signal conversion at a particular early location, ie near the leading edge of the bit cell. The mirror format provides a damping effect on any transformations occurring at the beginning of a one-bit interval following an interval containing a transformation at the center. Asymmetries in the waveforms produced by these rules can introduce DC into the encoded signal, and the codes used in this device, commonly referred to as mirror "squared" codes, are
It does this without the need for any large amounts of memory or speed changes in encoding/decoding.

Encoder circuit 96 also generates a unique Sync word in the form of a 7-digit binary number, 6SC.
and inserts Sync words on alternate lines at precise locations determined by the 1/2SC clock signal. In the record mode of operation, the clock signal generated from the sync component of the input video signal by reference logic circuit 125A is provided by encoder switch 126 to encoder circuit 96 where the horizontal Sync pulse of the video signal was previously located. inserted at roughly corresponding locations
Causes Sync. In other operating modes,
The 6SC and 1/2SC clock signals are supplied to the reference logic circuit 12.
5B and reference clock generator 98 from the synchronous component of the station's reference color black video signal. The encoder is
HSync related Sync words are gated to the data stream on alternate television lines at appropriate times with respect to the regenerated subcarrier phase.

Data track information recorded on the data tracks of disk drive 73 is also encoded by encoder 96 prior to re-recording. This data track information is provided by computer control system 92 via its data track interface 120.

In FIG. 9B, the encoded digital data stream produced at the output of encoder 96 is applied to an electronic data interface 89, which is simply a splitting and buffering circuit, which interface is connected to disk pack 75. The encoded data is coupled to three disk drives 73 for permanent recording. Each disk drive receives encoded digital data from an electronic data interface 89 and includes a recording amplifier circuit 153 and a head switch circuit 97 for recording it on the associated disk pack 75.
At the same time, it receives reproduced or detected data from the reproduction amplifier circuit 155 and the head switch circuit 97, and sends it to the data selection switch 128.
send to Furthermore, disk drive interface 1
1 receives multiple servo reference signals through an electronic data interface and sends them to the timing generator (39th servo reference signal) of the disk drive control circuit.
Figure). This signal is selected by computer control system 92 from either reference logic circuit 125A or 125B. The timing generator coordinates the operation of the disk drive system using multiple servo reference signals so that the recording and playback operations and rotational position of the disk pack 75 within the disk drive 73 are synchronized to the appropriate signal system timing reference. time.

The disk drive control circuit returns the pre-record timing signal and data timing signal to the signal system's electronic data interface 89 via the disk drive data interface 151. In the particular embodiment of the device described herein, four fields
Only two of the color code sequences of the NTSC color television signal are recorded, each of the two fields being recorded during a separate revolution of disk pack 75. Immediately prior to the recording of the two fields of video signal, a pre-recorder timing signal is generated and coupled electronically to data interface 89. This interface sends a pre-record timing signal to encoder 96 to cause generation in the apparatus described herein for an interval corresponding to two fields of data corresponding to a color brat digitally defined by a logical zero. Two field intervals of color black data are returned via the interface for recording into the data bag at the selected track location for recording the video data and its associated data track information. The recording of the two fields of color black data occurs during the two revolutions of disk pack 75 immediately preceding the two revolutions in which the two fields of video data are recorded. This conditions the track location for subsequent dual recording of video and data track data.
Double recording of the previously recorded digital data with new digital data is performed to erase the previously recorded digital data and leave a recorded signal that provides a sufficient S/N ratio to be simultaneously reproduced. Therefore, the pre-record operation cycle can be eliminated from the recording of two fields of video data and associated data track data, which takes place in only two revolutions of the device and disk pack 75.

The data timing signal is the digital data
During the second or last field of the two fields, the data track information is returned to the electronic data interface to time the generation and recording of the information. The signal starts after the vertical Sync that occurs between two fields of digital data, and
The pulse ends at the end of the second field. It is during this interval that data track information is recorded on the disk tracks of disk pack 75. Electronic data interface 89 couples the returned data timing signals to data track interface 120 of computer control system 92 for identifying data track recording intervals to the system. In response, computer control system 92:
Performs functions related to data track information, including providing data track information associated with recorded video data on designated tracks of a designated disk pack to the signaling system. encoder 96
receives the data track information and processes it as described in the text for sending to disk drive 73 for recording simultaneously with the last field of video data.

The recording and reproducing amplifier circuits 153, 155 and the head switch circuit 97 of the device described in the main text,
The disk drive unit control circuit includes a regenerative amplifier circuit 15.
5 and head switch circuit 97 are configured to be activated to reproduce data from the associated disk pack 75 at all times except when a recording operation is in progress. Thus, except during recording operations, reproduced data is always received by disk drive section interface 151, which in turn always provides reproduced data to data selection switch 128. To record data, a recording command given by the disk drive section control circuit is coupled to the recording/reproducing amplifier circuits 153 and 155 to activate the recording amplifier circuit 153 and disable the reproducing amplifier circuit 155. The disk drive control circuit also provides a 30 Hz head switch signal to the head switch circuit 97 during a recording operation to direct the data stream to the head switch circuit 97.
The two consecutive fields are connected to one set of heads during a first field and to a second set of heads during a second field. The 30 Hz head switch signal is continuously available and is similarly used during playback operations to control the head switch circuit 97 to direct the playback amplifier circuit 155 to two sets of signals for playback of both fields of the desired video data signal. Switch between heads.

Returning to FIG. 9A, during a regeneration operation, reference input circuit 97B, in conjunction with reference logic circuit 125B, produces a regenerated subcarrier frequency for application to reference clock generator 98, which in turn produces a regenerated subcarrier frequency for application to reference clock generator 98. It has outputs of 6SC, 1/2SC, and H/2 and other timing signals to provide base timing for. Clock and timing signals, including the reference H/2 signal, are synchronized with the reference color subcarrier to facilitate processing of the reproduced video signal. The reference H/2 signal is determined with respect to the particular phase of the reference color subcarrier in the first line of alternating fields of the reference color black video signal. The output of the reference clock generator inserts blanking, performs selective bit muting, and generates signals when the disk drives and associated heads coupled to the playback channel are moved between track locations. A data detector, time base collector 100, data transfer circuit 12, in addition to a blanking insertion dot mutating circuit 127 that provides the selected image frame video signal for output by the system.
9. To use the redefined reference H/2 signal provided to the saturation separator and processor 101 in the data decoder and time base collector 100, the synchronization word included in the alternating playback of the two video signals is the static reference HSync. incorrectly located with respect to. This can cause jitter in the displayed video image if not corrected. The above-mentioned synchronization error occurs when the blanking insertion bit muting circuit 127 at the front stage of the digital-to-analog exchange appropriately inserts a correction delay into the signal line when reproducing two field video signals alternately. It will be corrected accordingly. Reference clock generator 98 determines the color frame rate, H drive and field index signals provided by reference logic circuit 125B, and the reference color subcarrier signal. Determine which playback of a sequence of two field video signals requires a delay. In response to this confirmation, the reference clock generator generates a frame delay switch signal which is applied to the blanking insertion bit mutating circuit 127 to control correction delay insertion. The 8 bit digital information is then provided to a digital to analog converter and Sync and burst insertion circuits 102,130. Additionally, during the transfer and diagnostic mode of operation, reference clock generator 98 provides a base timing clock to encoder 96 via encoder switch 126 as shown.

During playback operations, a 10-bit parallel data stream comprising 8-bit video data, valid bits, and data from the data track being played from the disk pack is generated as shown in FIGS. 24-28.
The outputs of the three disk drives are amplified, equalized and detected by the circuitry shown and described with respect to FIGS. A data selection switch 128 is provided which can switch to one or more of the channels. Thus, the data selection switch can switch information from disk drive No. 1 to channel A while simultaneously providing a data stream from another disk drive to another channel. Information from two drives cannot be applied to one channel at the same time, but vice versa. The data selection switch 128 is comprised of a known switching circuit which will not be described in detail in this text.

Each of the detected 9-bit streams of video and integrity data from data selection switch 128 is then provided to nine separate data decoders and timebase collectors 100, which decode the data and then individually The nine data streams are time-base corrected with respect to a common H/2 reference defined with respect to the phase of the regenerated reference subcarrier to eliminate timing errors that may be present in the nine lines of data, i.e. each nine
Align all Sync words so that the parallel bytes of bits consist of the correct 9 bits of data. Other bit streams from the data track are coupled only to the decoder portion of the decoder/time base collector circuit 100 by the data selection switch 128, and the decoded data track information is
It is coupled to data track interface 120 for delivery to CPU 106. The time base corrector uses a continuous phase clock to perform its correction. However, this data is again retimed with respect to the PALE clock by the data transfer circuit 129, i.e. the phase of the signal is changed by reclocking on each horizontal line, so that the 8-bit data stream coming from the data transfer circuit is valid. This results in a PALE processed signal gain. The data transfer circuit 129 also performs validity checks on the off-disk data and individually identifies when an error occurs by substituting bytes detected as being in error with the most likely previous byte. Perform error masking for byte errors. Thus, the substituted byte is the third previous byte, which is the most recent sample assumed to have the same phase relationship to the SC.

The output of the data transfer circuit 129 is transferred to the encoder switch when the video information needs to be viewed in the opposite direction to be recorded on another disk drive (transfer). 126) is provided to the chroma separator and processing circuit 101. The chroma separation and processing circuit 101 operates in a digital state and separates chroma information from luminance using a comb filter technique and inverts the chroma information in alternate frames to form a four-field composite NTSC signal. , this signal is then provided to a video playback output circuit 127 which inserts a reference black level during the blanking period, a gray level signal during the interval between the playback of successive stills, and as needed. Perform bit muting operations. This bit muting effectively mutes which bits of the 8-bit television signal by blocking the data bitstream, and by doing so, results in exaggerated tones, ghost-like images, etc. Achieving extraordinary visual effects in television signals. The output from the blanking insertion and bit mutating circuit 127 is the output from the digital-to-analog converter 10 after this point.
given to 2. Digital to analog converter includes blanking insertion and bit output circuit 1
27, converts the data to its analog form, and inserts the Sync and burst components of the signal to produce a total composite analog television signal.

While the foregoing generally describes the general operation of the signaling system, FIGS. 9A and 9
A more detailed description of each block included in Figure B is as follows:
Each circuit is described in terms of its own separate functional block diagram or specific electrical diagram. Also, when functional block diagrams are used to describe the operation of the separate blocks of FIGS. 9A and 9B, electrical operational diagrams corresponding to the more detailed block diagrams are also included.

Reference logic circuits 125A, 125 shown in FIG. 7A
B receives various signals from input circuits 93A or 93B relating to horizontal and vertical synchronization signals, regenerative subcarriers, etc., and generates a number of clock and timing control signals, respectively, used in the operation of the embodiment device. Furthermore, a computer control device 9
2 provides control signals to logic circuits 125A and 125B, which generate servo synchronization signals in accordance with operations performed by the embodiment device, such as recording, playback, transfer, etc. These reference logic circuits are essentially the same, one used with video input circuit 93A and the other with reference input circuit 93A.
3B, both reference logic circuits are made to have somewhat different functions during different operations of the device such as recording, playback, transfer, etc. circuit 125A
and 125B perform different functions, so different inputs go into each, and not all outputs from each are used.

The operation of the reference logic circuit will be described below with reference to the functional block diagram of FIG. 8A, which has a horizontally extending dotted line approximately in the center. As shown, the upper portion of this circuit is used only during recording operations, and the lower portion is used during recording, playback, and other operations performed by this signal system. The function of the upper portion is to generate various phase-locked clock signals for recording operations using the regenerated subcarrier generated by video input circuit 93A from the color burst as described above. This circuit also generates an asymmetric PALE flag signal at a rate of H/2 that is used in this circuit to alternating the phase of the analog-to-digital converter sampling clock on a continuous horizontal line for the reasons discussed above. do. This PALE flag is also provided as an output of the reference logic circuit 125B for use in other parts of the signal system, primarily in the part used for processing the reproduced signal. This circuit also generates a set of three pulses at 15 Hz that is multiplexed with the H synchronization signal used to control the disk drive servo to generate a drive synchronization signal for the servo control operation of the disk drive motor. Occur. Other timing control signals are generated by reference logic circuit 125B as described below.

Looking at the upper part of Figure 8A, the reference logic circuit 1
A subcarrier signal (SC) from video input circuit 93A for 25A or reference input circuit 93B for reference logic circuit 125B is applied to line 300 which enters phase comparator 302. The output of this comparator appears on line 303 and adder 3
04's first input. Adder 304 has a second input on line 305 extending from integrator 306 . Precision digital burst phase decoder 3
07 receives the actual digitized video data taken from the output of analog-to-digital converter 95 on line 308, and decodes whether the sampled burst was done in the correct phase to ensure that the video signal is always correctly sampled. The integrator 30 is connected to the integrator 30 via line 309 for use in adjusting the phase of the sample clock so that the
A + or - error signal is generated for 6. The output of summer 304 appears on line 310 and is applied to loop amplifier and filter 311. This is connected to the voltage controlled oscillator 3 by a line 313 extending to one of the two failed lamp drivers 314.
Connect to 12. The output of oscillator 312 appears on line 315 at a frequency of 6SC, which in turn feeds a divide-by-6 counter 316 and a divide-by-2 counter 3 which provides a PALE clock output on line 318 at a frequency of 3SC.
Added to 17. Divide-by-6 counter 316 provides an output of the SC frequency on line 319, which is applied to Divide-by-2 counter 320 and the other input of comparator 302. The output of counter 320 is a 1/2SC signal, which appears on line 321 which extends to pulse transformer 322 which is used to set and reset the divide-by-two counter on alternating lines.
The control signal for this is provided on line 323 as a H/2 rate signal provided by PALE flag generator 324, as will be described below.

The operation of the upper part of this circuit is such that the voltage controlled oscillator 312 outputs a signal with a frequency of 6SC, which is precisely controlled so that the sampling performed by the A/D converter 95 is always performed correctly and in the same phase as the color burst synchronization signal. This is what happens in This is important given that the phase of the sampled video ultimately determines the color produced by the example device. Thus, phase comparator 302, which receives the split output of VCO 312 on line 319 at one input, compares the phase of its output to the phase of the video or reference subcarrier synchronization signal on line 300 entering the other input. Provide a phase lock loop that locks near the target. The divided output of VCI 312 produces an SC signal that is typically within about 10 degrees through this phase lock loop. However, A/
The digitized video output of D converter 95 is passed to precision digital burst phase decoder 307.
via line 308, which is integrated by integrator 306 to provide an average value that is applied to adder 304, enabled by a precision burst sampling gate signal coming from video input circuit 93A via line 307a. generates an error signal that is extracted during the burst interval of the video. As a result, the output voltage level of the loop amplifier 311 that controls the VCO 312 is changed to the decoder 30.
7 is adjusted to compensate for variations in the sampling time of the video signal as reflected in the burst samples provided at 7. These burst samples represent the same value for all lines unless there is variation in sampling time. By examining the sampled data that actually occurs at the output of the A/D converter, it is possible to accurately determine whether these samples were taken at the correct locations, and in this way divide-by-two counter 317
The VCO output on line 315 applied to the VCO output on line 318 controls the A/D converter 95 to keep the sampling in the correct phase.
Generates PALE3SC clock. Precision digital phase decoder 307 effectively corrects errors caused by temperature drift, etc. on the order of 5° to 10°. In this regard, the phase of the video (or reference) subcarrier synchronization signal on line 300 is
provides a basic lockup for the reference logic circuit 123B, and the fine correction occurring on line 305 in reference logic circuit 123B is configured to vary the phase by a few degrees, or about 20 degrees.

For the bottom portion of FIG. 8A, the PALE flag generator 324 is set high to switch a switch 325 that distributes the 1/2SC pulse to the set and reset terminals of the divide-by-two counter 317, which generates the PALE clock on the output line 318. /2 speed
The PALE flag that generates the PALE flag signal is the 8th
Change the state for each line as described for diagram B. The PALE flag signal is asymmetrical so that even if the phase of the 3SC PALE clock is reversed during the video periods of alternate lines, it will not be reversed during the video signal burst intervals. The effect is thus that only the portion of the line after the burst is sampled with a clock signal whose phase is inverted on alternate lines, ie, an asymmetric signal. PALE flag generator 3 as shown in Figure 8A
24 receives the input from the H drive video input (or reference) input circuit 93A (or 93B) provided on line 326, the field index pulse on line 327, and the burst flag on line 328. The burst flag is set so that the sampling phase of the burst must not be changed due to the operation of the burst phase decoder 307 in the upper part of FIG. 8A.
The PALE flag generator does not issue a PALE flag signal on line 323 until after the burst has occurred. PALE flag generator 324 provides an H/2 rate transfer reset pulse, which is transmitted on line 324a.
is sent to the encoder switch 126 via the encoder switch 126.
The encoder switch uses this pulse during data transfer operations to generate a signal used thereby to reset the encoder 96's sync word inserter.

The H drive and field index signals are applied to a drive servo sync generator 330 having an output extending via line 332 to a drive sync switch 331, which is in turn driven by a drive sync source command on control line 333 from computer control system 92. When commanded, line 3 for each disk drive 73
A basic drive synchronization signal is provided on 34. These synchronization signals are necessary for all operations that transfer information between disk pack 75 and the signaling system. Computer control system 92 distinguishes whether a recording or playback operation is desired.
The synchronization information takes the form of a multiplexed synchronization signal,
Line 33 extending to the disk drive unit
Occurs in 4. This signal includes a set of three continuous wide pulses and a horizontal sync pulse (H speed) to indicate the first field being recorded or played back at a set speed of 15Hz, and controls the spindle servo motor. used for. Color frames and associated synchronization signals are also generated for use by the reference clock generator in generating control signals for controlling the servo drives and for use during playback operations. Color frame related synchronization signals are obtained from color frame generator 301. This receives a 30 Hz field index pulse signal via line 327 and divides it in half to create a 15 Hz color frame signal. This color frame signal is line 3
29 to disk drive 73 and reference clock generator 98.

Specific circuitry that can be used to perform the operations of the block diagram of FIG. 8A is shown in FIGS. 9A-9D. These diagrams together form the electrical circuit of the reference logic circuit. The operation of this circuit is generally similar to that described in FIG. 8A and will not be described in detail here. However, with respect to the digital burst phase decoder 307 in the upper part of FIG. 9A, the A/
The digitized video subcarrier synchronization signal or color burst in the form of 8 bits taken from the output of D converter 95 is transferred to shift register 3.
occurs on line 308 which connects to arithmetic logic unit 335 which is connected to 36. shift register 33
6 is generally 33 activated when a precision burst sampling gate signal is input via line 307a.
7 and together with arithmetic unit 335 performs the arithmetic steps necessary to determine the sign of the phase of the digitized color burst on line 309. The sampling error, if any, is determined by examining the 90° quadrature component of the sample, which would be zero if the sampling was taken at the proper phase of the subcarrier color burst signal. In detail, this component is sample X1,
When X2 and X3 are 120° apart, the function X1-1/2
Proportional to (X2+X3). Clock logic circuit 33
7 is an arithmetic unit 335 and a shift register 33
Line 3 where 6 shows the actual sample phase error
Execute a sequence that allows calculations to be made to generate a + or - signal on 09.

Specifically, a precision burst sampling gate signal at pin 72 energizes and enables the decoder at the beginning of each horizontal line of the video signal. The first sample of the color burst of the video signal after the precision burst sampling gate signal is 0 or 0
, the color burst axis cross-axis position is very close to . The next two color bursts in the video signal
The two samples represent (or very close to) the 120° and 240° color burst phase points, respectively, as described above in connection with Figure 7C(1). The amplitude of the burst is expressed by the formula Asin(WZ+θ). where θ is the offset from the desired 0°, 120°, and 240° sampling phase position. This equation can be decomposed into sine and cosine components, Asin wt
It is expressed as cosθ+Acos wt sinθ. If θ is close to 0, the cosine value of θ will be approximately equal to 1, and the sine value of θ will be approximately equal to θ, so the above equation can be approximated as Asin wt+Aθcos wt. Therefore,
The sampling error θ can be determined by demodulating the cosine component of the above approximation (this is the component shifted by 90° of the sampled color burst).

The circuit 100 including the decoder of FIG. 7A demodulates the sample values by multiplying the sample values X1, X2, and X3 by the numbers cos0°, cos120°, and cos240°, respectively, in a binary system and adding the results to each other. Achieve.
Since cos0°=1, cos120°=1/2, and cos240°=−1/2, θ●X1+1/2X2−1/2X3 is obtained. Since only the sign of θ matters, the proportionality constant does not matter.

In FIG. 9A, a circuit 324 is provided on line 323 for generating a PALE flag signal;
The H drive signal is inverted by inverter 342 and applied via line 338 to the clock input of FF 339. This FF is a divide-by-2 frequency divider with an output line 340 connected to the input of a second FF 341 that is clocked by a burst gate or flag signal on line 328. Line 340 extends to NAND gate 343 as does output line 344 from FF 341. The operation of PALE flag generator 324 will be explained with reference to the timing diagram of FIG. 8B. Here, Fig. 8B (1)
the H drive signal (line 326), the signal on line 340 in Figure 8B (2), and the signal on line 340 in Figure 8B (3).
the signal on line 344, the burst gate clock on line 328, and the burst gate clock on line 328.
Figure B (5) shows the outputs of the NAND gates on line 345, respectively. on line 323
The PALE flag signal is the signal on line 345 inverted by inverter 346. PALE
The flag signal occurs at a rate of H/2, but the 8th B
Figure (5) shows that the output of FF 341, which appears on line 344 and is applied to NAND gate 343, is
It is shown as asymmetric because it is delayed with respect to the output of 1FF339. This is because the FF341 is clocked not by the H drive but by the burst gate.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the general appearance of an apparatus embodying the invention, including an internal access station and two disk drive units, and FIG. FIG. 3 is an enlarged perspective view of a typical remote access station that can be used; FIG. 3 is an enlarged partial view of the keyboard of the internal access station of FIG. 1, particularly showing the various keys and bars used by the operator during operation; FIG. 5 is a simplified functional block diagram of the overall configuration of the embodiment device, FIG. 5 is a functional block diagram showing a simplified signal path passing through the embodiment device during recording operation, and FIG.
The figures are functional block diagrams showing simplified signal paths passing through the embodiment device during playback operation, Figures 7A and 7.
FIG. 7B is a more detailed block diagram of the signal system of the embodiment device; FIG. 7C is a timing diagram showing the sampling and phase relationships of the television signal occurring at various locations in the signal system of the embodiment device;
Figure A is a block diagram of a reference logic circuit that is part of the signal system shown in Figure 7 and incorporates the present invention, and Figure 8B is a block diagram for the PALE flag generator included in the reference logic circuit of Figure 8A. Timing diagrams, Figures 9A, 9B, 9C, and 9D are 8A
2 shows a detailed electrical circuit diagram of the reference logic circuit shown in the figure; FIG. In the figure, 95 is an analog-to-digital converter, 30
2 is a phase comparator, 307 is a precision digital burst phase detector, and 312 is a voltage controlled oscillator.

Claims (1)

Claims: 1. An analog information signal having an associated carrier signal is sampled at a desired precise phase position with respect to the carrier signal to provide discrete samples of the information signal with respect to the desired precise phase position. A sampling device comprising: (a) sampling means for sampling the information signal and providing the individual samples in response to receiving an applied clock signal; (b) generating a clock signal at the output; (c) a phase control signal for controlling the phase of the output of the clock signal generating means so as to sample the information signal with respect to the desired precise phase position; (d) The control signal means compares the phase of the carrier signal with the phase of the output of the clock signal generation means to determine the phase of the output of the clock signal generation means. (e) the control signal means further includes means for providing a first error signal for controlling the phase of the clock generation means to maintain a generally phase-locked relationship with the carrier signal; means for creating a second phase error between the actual phase position of the sample and the desired precise phase position, the control signal means outputting a signal representative of the second phase error to the clock signal. adjusting the phase of the output of the clock signal generating means to reduce the second phase error to substantially zero, the individual samples of the information signal being substantially at the desired precise phase position; A sampling device characterized in that the sample is taken with respect to the sample.