JPH0441674U - - Google Patents

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Publication number
JPH0441674U
JPH0441674U JP8301090U JP8301090U JPH0441674U JP H0441674 U JPH0441674 U JP H0441674U JP 8301090 U JP8301090 U JP 8301090U JP 8301090 U JP8301090 U JP 8301090U JP H0441674 U JPH0441674 U JP H0441674U
Authority
JP
Japan
Prior art keywords
radar
primary
detected
response data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8301090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8301090U priority Critical patent/JPH0441674U/ja
Publication of JPH0441674U publication Critical patent/JPH0441674U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例によるレーダ信号
処理装置を示す構成図、第2図と第3図は第1図
の動作を示すフローチヤート、第4図は従来の装
置を示す構成図である。 図において、1はSRバツフア回路、2はSI
Fバツフア回路、3はSR/SIF回路、4はマ
イクロコンピユータを示す。なお、図中、同一符
号は同一又は相当部分を示す。
FIG. 1 is a block diagram showing a radar signal processing device according to an embodiment of this invention, FIGS. 2 and 3 are flowcharts showing the operation of FIG. 1, and FIG. 4 is a block diagram showing a conventional device. be. In the figure, 1 is the SR buffer circuit, 2 is the SI
3 is an SR/SIF circuit, and 4 is a microcomputer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 振幅モノパルス仰角検出のレーダ装置において
、1次レーダの検出目標が順次書込まれるSR検
出回路、2次レーダの検出目標が順次書込まれる
SIF検出回路、1次レーダで検出した目標と2
次レーダで検出した目標とを合成するSR/SI
F合成回路、及び2次レーダの応答データの1種
であるモードC応答データ(航空機の高度を示す
)を使用して1次レーダの送信ビームの仰角を検
定する仰角検定回路とを備えたレーダ信号処理装
置。
In a radar device that detects amplitude monopulse elevation angles, there is an SR detection circuit in which targets detected by the primary radar are sequentially written, an SIF detection circuit in which targets detected by the secondary radar are sequentially written, and a target detected by the primary radar.
SR/SI that combines with the target detected by the next radar
A radar equipped with an F synthesis circuit and an elevation angle verification circuit that verifies the elevation angle of the primary radar's transmission beam using mode C response data (indicating the altitude of the aircraft), which is a type of response data of the secondary radar. Signal processing device.
JP8301090U 1990-08-04 1990-08-04 Pending JPH0441674U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8301090U JPH0441674U (en) 1990-08-04 1990-08-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8301090U JPH0441674U (en) 1990-08-04 1990-08-04

Publications (1)

Publication Number Publication Date
JPH0441674U true JPH0441674U (en) 1992-04-08

Family

ID=31630321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8301090U Pending JPH0441674U (en) 1990-08-04 1990-08-04

Country Status (1)

Country Link
JP (1) JPH0441674U (en)

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