JPH0442667A - Video signal clamp circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal clamp circuit used in a video signal processing device in a television receiver or the like.

[Prior art 1] Figure 3 is a block diagram showing the configuration of a conventional video signal clamp circuit. In the figure, +11 is a video signal input terminal, (21, (3) is a buffer amplifier, and (4) is a It is a capacitor.

(5) is an A/D converter that converts the video signal into a digital signal. (6) is a sampling circuit which samples a predetermined portion of the digital signal, that is, the value at the clamp position. (7) is a subtraction circuit that calculates the difference between the sample value output from the sample circuit (6) and the reference value output from the reference value setting circuit (I2).

(8) is a l)/A converter, and the above subtraction circuit (7
) is converted into an analog signal. (
9) is an amplifier circuit, and (10) is a switch that determines the clamp timing, which is controlled to be 0NOFF by the clamp pulse output from the clamp pulse generating circuit (I3). (11) is a video signal output terminal.

Next, the operation of the above configuration will be explained.

A video signal input from an input terminal (1) is amplified by a buffer amplifier (2) and then input to a buffer amplifier (3) through a capacitor (4).

The signal amplified by this buffer amplifier (3) is
A predetermined portion of the value of this digital signal, that is, a value at the position of the crank buoy, is sampled in a sampling circuit (5).
The figure shows the relationship between the clamp position and the video signal.

The values sampled in this way are processed by the subtraction circuit (7
), the difference with the reference value output from the reference value setting circuit (12) is calculated, converted into an analog signal through the D/A converter (8), and then input to the amplifier circuit (9) where it is amplified. Ru. The amplified difference signal (A) operates as a voltage source, and when the switch (10) whose ON/OFF control is controlled by the clamp pulse output from the clamp pulse generation circuit (13) is closed, the capacitor (4) is After charging, clamping operation is performed. Here, each of the above components (31, +51. (61, +7
1. (8), +91. +121 constitutes a feedback loop, so the level at the clamp position is gradually converged to the reference value and output from the output terminal (11).

[Problems to be Solved by the Invention] Since the conventional video (No. In other words, settling time, overshoot, etc., and final convergence accuracy are determined by the characteristics of the feedback loop. Therefore, if high performance is required for both transient response and convergence accuracy, the design should take into account the characteristics of the feedback loop. There were drawbacks that made it very difficult.

This invention was made to solve the above-mentioned problems, and can improve both transient response characteristics and convergence accuracy, and is not affected by feedback loop characteristics and can be easily designed. The purpose of this invention is to provide a video signal clamp circuit that can

[Means for Solving the Problems] The video signal clamp circuit according to the present invention is characterized in that it is configured to add a subtraction signal between a voltage value sampled from a predetermined position in the video signal and a reference value to the video signal. shall be.

[Operation] According to the present invention, by adding an error signal resulting from subtraction between the sampling value of the video signal and the reference value to the video signal, convergence at the output terminal is accelerated and the influence of the characteristics of the feedback loop is reduced. It is possible to improve convergence accuracy and simplify the construction of loops.

[Embodiment of the Invention] An embodiment of the present invention will be described below based on the drawings.

1M is a block diagram showing the configuration of a video signal clamp circuit according to an embodiment of the present invention;
) to (13) are the same as those of the conventional example shown in FIG. 2, so the corresponding parts are given the same reference numerals and detailed explanation thereof will be omitted.

In the 1st M, (14) is an addition circuit, and a subtraction circuit (7
) is added to the digital signal output from the A/D converter (5).

Next, the operation of the above configuration will be explained.

A video signal (V) input from an input terminal (1) is amplified by a buffer amplifier (2) and then input to a buffer amplifier (3) through a capacitor (4). The output of this buffer amplifier (3) is digitized by an A/D converter (5).

The digitized data is sampled in the sampling circuit (5) at the portion shown by the timing of the clamp pulse in C1 (point S) in Figure 2 (Fig. 2), and the sampled value is subtracted from the reference value in the subtraction circuit (7). The difference signal, that is, error data is extracted.This error data is converted into an analog signal by a D/A converter (8), and then input to an amplifier circuit (9) and amplified.

The amplified difference signal (Al) charges the capacitor (4) through Sui-Sochi (10).

That is, as shown in FIG. 2, the clamp pulse fc
) in the video signal fVl becomes "11" at the point T[S, and at the same time, the switch (lO) is turned on.At this time, the capacitor (4) is charged by the output (Al) of the amplifier circuit (9). , the input of the buffer amplifier (3) is (Al
is fixed to the value of Since this configuration is a feedback loop, once a certain period of time has passed, the voltages at the 8 points in Figure 2 can be adjusted to the specified standard using the human power of the buffer amplifier (3). 1! converges to the value.

On the other hand, the video signal digitized by the A/I) converter (5) is input to the adder circuit (14), where
It is added to the output of the subtraction circuit (7). This results in
The output of the addition circuit (14) becomes the reference value at point S in Figure 2, and during other periods, it becomes a signal to which a constant value corresponding to the difference from the reference value at 8 points obtained by the subtraction circuit (7) is added. becomes. Therefore, the signal output to the output terminal (11) is (3).

+51, +6), (71, (8), +91
, 1121 is converged to the target value before convergence, and even if there is a steady-state error in the feedback loop, the output is output from the output terminal +11).

The steady state error will be canceled out.

[Effects of the Invention] As described above, according to the present invention, by adding the error signal extracted from the feedback loop to the video signal, convergence can be accelerated and transient response characteristics can be improved, and the loop characteristics can be improved. Convergence accuracy can also be improved without being affected. Further, since the influence of the loop characteristics is small, the design of the loop becomes easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a video signal clamp circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing operation timing, and FIG. 3 is a block diagram showing the configuration of a conventional video signal clamp circuit. be. (5)...A/D converter, (8)...Sample circuit, (7)...Subtraction circuit, (1G)...Switch, (14)...Addition circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) It is characterized by comprising means for sampling the voltage at a predetermined position in the video signal, means for subtracting the sampled voltage value from a reference value, and means for adding the result of the subtraction to the video signal. video signal clamp circuit.