JPH0442684A - Video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To omit a selector and to reduce the circuit scale by increasing bits of an address input of a ROM of a noise reduction circuit by one and outputting data from a frame memory as it is from a noise reduction circuit. CONSTITUTION:An input signal is fixed to a prescribed value in the still picture mode and a signal switched depending on the normal reproduction mode and the still picture mode is used for part of address input of a ROM 14. That is, output control of a latch at the input of a noise reduction circuit is controlled in the still picture mode and the data from a frame memory 12 is outputted as it is from the noise reduction circuit by having only to add one bit to the address input of the ROM 14. Thus, a selector or the like is omitted and the circuit scale is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal recording and reproducing device such as a video tape recorder (hereinafter referred to as VTR) and a video disc player. This relates to technology for reducing

[Prior Art] Fig. 4 shows a digital noise reduction circuit (hereinafter referred to as noise reduction) in the time axis direction that is applied to a playback system of a video signal recording and playback device, and removes noise components that are Φ-folded into a video signal. In the figure, (I9) is a multiplier that multiplies the digital input signal by a constant K (0≦K<+). (18) is a frame memory, which delays input signal No. 3 by one frame and outputs it. (16) is a subtracter which subtracts the output of the frame memory (18) from the human input signal. (I7) is also a subtracter, which subtracts the output of the multiplier (!9) from the human input signal.

Transfer function H(z) of the noise reduction circuit with the above configuration
becomes H(zl = (]-K)/(1-Kz), which becomes a low-pass filter in the time axis direction.

In such a low-pass filter in the time axis direction,
Although it has an excellent noise reduction effect on still city images, it causes blurring in the video parts. Therefore, there is a method of changing the gain of the multiplier (19) in the range of 0≦K<1 according to the movement, but this method will be described later.

FIG. 5 shows a noise reduction system having the above-mentioned principle configuration.
1 is a block diagram showing the configuration of a conventional VTR playback system in which a color signal noise reduction circuit is applied;
1) is a magnetic tape which is a recording medium, (2a), (2
b) is a rotary head for recording and reproducing video signals, (3) is a head amplifier, (0 is an FM demodulating FM signal to be reproduced)
demodulation circuit; (5) is an A/D converter that performs A/D conversion;
(8) is a luminance signal (Y) and a color difference signal (R-Y), (B-
Y), time axis extension is performed on each, and a single signal (Y) restored to the original length of one horizontal scanning period and a line sequential color signal (R-Y/CB-Y) are output. This is a reproduction signal processing circuit.

(20) is a noise reduction circuit that reduces the noise component of the above-mentioned line sequential color signal (RY)/(B-Y). (8) is a vertical interpolation circuit that restores color difference signals (R-Y), (B-Y) from line-sequential color signals (R-Y)/(B-Y), (9a), (9b), (9c) ) is a D/A converter that converts digital data into analog data.

FIG. 6 is a block diagram showing a specific configuration of the noise reduction circuit (20).
) is a latch made of an IC such as 74A3574, which latches 8-bit data of the line sequential color signal (RY)/(B-Y) output from the reproduced signal processing circuit (6) in FIG. A subtractor (10) to be described later.

Output to (11). (10) is a subtracter, which uses 8-bit digital data output from the frame memory (12), which will be described later, to generate the 8b output from the latch.
It subtracts the digital data of "it" and outputs 9-bit digital data. Note that the 9th bit, which is the MSB, is a sign bit, and when it is 'H', it indicates that the value is a negative value.

(1 is also a subtracter, and the above latch (21
), subtract the 8-bit data output from
Outputs digital data. (22) is a ROM, which outputs 8-bit data in response to a 9-bit address input. (12) is the 8bi of the subtracter (11) above.
This is a frame memory that outputs digital data of t after being delayed by one frame.

(23) is a switch, and when it is OFF, data is not written to the frame memory (12). (24) is a control circuit that receives the still image mode signal and receives the switch (2).
3) and a selector (25) to be described later. (25
) is a selector which selects the output of the subtracter (11) and the output of the frame memory (12) by the control circuit (20) and outputs either one.

Next, the operation of the configuration shown in FIG. 5 will be explained.

The line sequential color signal (
The 8-bit data of R-Y)/(B-Y) is input to the noise reduction circuit (20). The switch [23] in this noise reduction circuit (20) is VT
When R is in normal playback, it is in the ON state. In addition, the selector (25) is connected to the terminal (25al) when the VTR is in normal playback mode.
Select the output of

Input line sequential color signal (R-Yl/(8 of B-Yl)
bit data xi, noise-reduced output signal 8
Let Yl-2 be the output of the previous frame, that is, the 8-bit data output of the frame memory (12). -K.(X+ -Yi-2>), where i indicates the field number.

In the case of moving images, in order to prevent blurring due to temporal processing, X
If the value of i - Yi-2 is large, it is determined that it is a moving image, and it is necessary to change K. (Xi - Yi-2). If we set this as f (Xi -Yi-2), ROM +221 in Fig. 6 is this function r (Xi -Yi-2
).

In other words, when the 9biL output data of the subtractor (10) is input manually, 8bit data is output according to the value.6 Figure 7 shows an example of the functional form realized using this ROM (22). show.

Regarding the noise reduction circuit in the time axis direction, there are well-known sources such as "Digital signal processing of images" (written by Takahiko Fukinuki, published by Nikkan Kogyo Shimbun), Chapter 7, 3.3, pages 115 to 117. Therefore, detailed explanation will be omitted. Further, since the T'CI signal is well known, starting from Chapter 5, 2.3, pages 60 to 61 of the above-mentioned T'CI signal book, a detailed explanation will be omitted.

The output signal Yi whose noise has been reduced by the above method, that is, 8b of the line sequential color signal [1l-Yl/IB-Y)
The digital data of it is sent to the vertical interpolation circuit (8) in Figure 5.
After being manually inputted, it is converted into one color difference signal R-Y, B-Y, and then converted into analog data by a D/A converter (9b), (9cl) and output as a noise-reduced color difference signal.

Here, the operation of the noise reduction circuit (20) when the VTR shifts from the normal playback mode to the static IF picture mode will be explained.

When the VTR shifts from the normal playback mode to the still picture playback mode, the still picture mode signal changes from "L" to "H". When the control circuit (24) receives the signal, the switch (23) is first turned OFF and the writing to the frame memory (12) is stopped.Next, when the selector (25) is switched to the terminal (25b) side, The same data from the frame memory (12) is always read out from the output of the noise reduction circuit (20).

[Problems to be Solved by the Invention] Since the conventional video signal recording and reproducing site is configured as described above, when in the still image mode, it is possible to directly read data from the frame memory (12) of the noise reduction circuit (20). In order to read the data, the data output from the latch (21) is subtracted by the data output from the ROM (22), and the frame memory (12)
A selector (25) is required to switch and output the data directly outputted from the output terminal, and therefore there is a problem in that the size of one circuit becomes large.

This invention was made to solve the above-mentioned problems, and by simply adding one bit to the address input, data from the frame memory can be output as is, reducing the circuit size. The purpose of the present invention is to provide a video signal recording and reproducing device.

[Means for Solving the Problems] The video signal recording and reproducing device according to the present invention fixes the input signal to a constant value when in the still image mode, and sends a signal for switching between the normal reproduction mode and the still image mode to a ROM address. It is characterized in that it is configured to be input III.

[Operation] According to the present invention, by increasing the address input of the ROM of the noise reduction circuit by 1 bit, it becomes possible to output data from the frame memory as is from the noise reduction circuit, and the selector can be omitted.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of a reproducing system of a VTR for recording and reproducing TCI signals according to an embodiment of the present invention.
In the same figure, (1) and (2a).

(2b), (3) to (8), (8),
Since (9a), (9b), and (9c) are the same as the conventional example shown in FIG. 5, the same reference numerals are given to the corresponding parts and detailed explanation thereof will be omitted.

In FIG. 1, the only difference from the conventional example in FIG. 5 is the noise reduction circuit (26), and the specific configuration of this noise reduction circuit (26) is as shown in the block diagram in FIG. be.

In Figure 2, (lO) to (12), (21) are the sixth
Since they are the same as the conventional noise reduction circuit shown in the figure, they are given the same reference numerals and detailed explanation thereof will be omitted.

In Figure 2, (10 is for 1 obit input,
A ROM that outputs 8-bit data, with a subtracter (lO)
The function form for the 9-bit output and the function form for outputting the input data as is are set. (15) is a control circuit which receives the still image mode signal and latches the above latch (2).
The output data in step 1) is fixed and the ROM (14) is set to a function form in which the input data is output as is.

FIGS. 3(a) and 3(b) show the functional form realized by the ROM (14) when the address input (7) MSB is "H".

Next, the actual operation of the noise reduction circuit (2B) when the VTR shifts from the normal reproduction mode to the still picture mode will be explained using FIGS. 1, 2, and 3.

In the normal playback mode, the output control of the latch (21) is controlled by the control signal from the control circuit (15).
Therefore, the 8-bit input data of the line sequential color signal input to the latch (21) is directly input to the subtracter (lO
) and (11). Further, the above control signal is connected to the MSB of the address input of the ROM (14). When this control signal is “L”.

As in the conventional example, the 9-bit data corresponding to the output of the subtracter (10) is outputted to the ROM (14).

When the VTR shifts from the normal beef mode to the still picture mode, the still picture mode signal changes from "[,° to °H".

The control circuit (I5) receives this change and outputs the control signal as “[,
Change from ° to “H”. Therefore, the latch (21
) output control and ROM +141 M
SB becomes “H-” here.

The output control input of the latch (21) is “H”.
”, all 5biL output data of “H” regardless of the value of input data.

In addition, 8 bits output from the frame memory (12)
The subtracter (lO) subtracts the data of all 8 bits of the latch (21) that are "H", and the signal is stored in the ROM.
(14). The data input to this RoM (!4) is expressed as 255-M. Here M
is data output from the frame memory (12), and satisfies 0≦M≦255.

Tokorochi, the above ROM (14) When the MSB of the address input, that is, the signal input to the 10th bit, is "H" in the W3v4 display, the remaining 9 bits
The output is output as is as 8-bit data1
That is, as described above, since the data input to the ROM (14) is 255-M2O, the code bit of the 9th bit is always "O", and the value of the data does not change even if it is truncated.

The 8-bit data output from this ROM (14+) is input to the 8-bit data from the latch (21) in the subtracter (11).
Since all "H" data is subtracted from both "IT" and "H" data, the 8-bit data output from the subtracter (11) is the same as the data output from the frame memory (12).

That is, when expressed as a formula, 255-(255-M)=M.

After this data is written into the frame memory (12) again, it is read out with a delay of one frame, and the above series of operations is repeated. In this way, in still image mode,
The same 8-bit digital data of the line sequential color signal (R-Y)/(B-Y) is always outputted from the frame memory (12), and the vertical interpolation circuit (8) converts the color difference signals R-Y, B-Y into 8-bit digital data. -Y, then converted into analog data by D/A converters (9b) and (9cl) and output as color difference signals R-Y and B-Y.

Note that in the above embodiment, the case related to 8-bit data output from the reproduced signal processing circuit was explained.
The number of bits is not limited to 8 bits, but other bits may also be used.
In the case of t number, the address force of ROM f+41 is 1b.
Just by adding it, the same effect as in the embodiment F can be obtained.

In addition, in the embodiment described above, 74AS574 IC is used,
We have explained the case where the output control terminal is set to "H" and all bits output "H" data, but if the clear terminal of the 74AS 174 (7) IC is set to "L"
” and all bits output “Yes” data,
If the functional form realized by ROM +141 is set linearly, the output of the noise reduction circuit becomes the output of the frame memory, as shown in the following equation,
The same effects as in the above embodiment are achieved.

0- (0-M)=M In this case, the data input to the ROM is 0-M≦
Since it is O, a sign bit is required to indicate that it is a negative value, so the ROM output is output from the latch with all bits “
This results in an increase of 1 bit compared to the case where data of "H" is output.

Furthermore, in the above embodiment, the line sequential color signal (RY) /(
Although a case has been described in which a noise reduction circuit is provided for the B-Y signal, the same effects as in the above embodiments can be obtained also when a noise reduction circuit is provided for the -degree signal or the TCI signal.

Further, in the above embodiment, a noise reduction circuit using a frame memory has been described, but a field memory may be used as long as the same effect can be obtained.

Furthermore, in the above embodiment, the V for recording and reproducing the TCIM number
We have explained the case of TR, but V that incorporates a noise reduction circuit in the time axis direction using frame memory
As long as it is a TR, a VTR that adopts another recording method such as a two-channel three-segment method may be used, and other video signal recording and reproducing devices such as a laser disc can also produce similar effects.

[Effects of the Invention] As described above, according to the present invention, in the still image mode, it is possible to control the output of errors and hits in the input of the noise reduction circuit, and to add only one bit to the address input of the ROM. Since the structure is configured such that the data from the frame memory is outputted as is from the noise reduction circuit, a selector etc. can be omitted and the circuit scale can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a reproduction system of a VTR according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a digital noise reduction circuit in the time axis direction according to an embodiment of the present invention, and FIG. The figure shows the functional form of the ROM, Fig. 4 is a block diagram showing the principle of the digital noise reduction circuit in the time axis direction, Fig. 5 is a block diagram of the conventional VTR playback system, and Fig. 6 is the conventional VTR playback system. FIG. 7 is a block diagram showing the configuration of a digital noise reduction circuit in the time axis direction. FIG. 7 is a diagram showing the functional form of the ROM of the conventional digital noise reduction circuit in the time axis direction. (10) , (m...subtractor, (12)...frame memory (+4)...ROM, (15)...control circuit, (21)...latch, (2B)...・Noise reduction circuit. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a video signal recording and reproducing apparatus comprising a noise reduction means that performs noise reduction processing on a video signal during reproduction, and a mode switching means capable of switching between a normal reproduction mode and a still image mode, the noise reduction means at least 1
a memory capable of storing a video signal of a field period; input signal converting means for inputting a video signal and fixing an output to a constant value of high or low when the mode switching means is in a still image mode; 1. A video signal recording and reproducing device comprising: a ROM having a signal that is switched to high or low depending on a still image mode as part of an address input.