JPH044278U - - Google Patents
Info
- Publication number
- JPH044278U JPH044278U JP4653490U JP4653490U JPH044278U JP H044278 U JPH044278 U JP H044278U JP 4653490 U JP4653490 U JP 4653490U JP 4653490 U JP4653490 U JP 4653490U JP H044278 U JPH044278 U JP H044278U
- Authority
- JP
- Japan
- Prior art keywords
- signal input
- fet
- pole
- bias voltage
- protected unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
第１図はこの考案の実施例を示す回路図、第２
図は作用説明用の等価回路図、第３図および第４
図は従来装置の回路図である。
図中、１，２……入力端子、４……増幅器、６
……保護回路、Ｄ１，Ｄ２……ダイオード、Ｒ１
……抵抗、Ｑ１，Ｑ２……ＦＥＴ、＋Ｖ，−Ｖ…
…バイアス電圧である。
Figure 1 is a circuit diagram showing an embodiment of this invention, Figure 2 is a circuit diagram showing an embodiment of this invention.
The figures are equivalent circuit diagrams for explaining the function, Figures 3 and 4.
The figure is a circuit diagram of a conventional device. In the figure, 1, 2...input terminal, 4...amplifier, 6
...protection circuit, D 1 , D 2 ... diode, R 1
...Resistance, Q1 , Q2 ...FET, +V, -V...
...is the bias voltage.
Claims (1)
介設された抵抗と、上記被保護ユニツトの信号入
力側と所定のバイアス電圧を有する電源間に直列
的に接続されたダイオード及びＦＥＴとを備えて
なり、 該ＦＥＴはそのゲート側を一方の極となし、ド
レイン及びソース側を共通接続して他方の極とな
すとともに、同ＦＥＴと上記ダイオードが上記バ
イアス電圧に対してともに逆方向に配設されてい
ることを特徴とする信号入力部における保護回路
。[Claims for Utility Model Registration] A resistor interposed in the signal path from the signal input end to the protected unit, connected in series between the signal input side of the protected unit and a power supply having a predetermined bias voltage. The FET has its gate side as one pole, and its drain and source sides are commonly connected to make the other pole, and the FET and the diode are connected to the bias voltage. A protection circuit in a signal input section, characterized in that both are arranged in opposite directions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4653490U JPH0740220Y2 (en) | 1990-04-27 | 1990-04-27 | Protection circuit in signal input section |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4653490U JPH0740220Y2 (en) | 1990-04-27 | 1990-04-27 | Protection circuit in signal input section |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH044278U true JPH044278U (en) | 1992-01-16 |
| JPH0740220Y2 JPH0740220Y2 (en) | 1995-09-13 |
Family
ID=31561698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4653490U Expired - Fee Related JPH0740220Y2 (en) | 1990-04-27 | 1990-04-27 | Protection circuit in signal input section |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0740220Y2 (en) |
-
1990
- 1990-04-27 JP JP4653490U patent/JPH0740220Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0740220Y2 (en) | 1995-09-13 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |