JPH0442943Y2 - - Google Patents
Info
- Publication number
- JPH0442943Y2 JPH0442943Y2 JP1984062036U JP6203684U JPH0442943Y2 JP H0442943 Y2 JPH0442943 Y2 JP H0442943Y2 JP 1984062036 U JP1984062036 U JP 1984062036U JP 6203684 U JP6203684 U JP 6203684U JP H0442943 Y2 JPH0442943 Y2 JP H0442943Y2
- Authority
- JP
- Japan
- Prior art keywords
- printed
- wiring
- single electrode
- mounting
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
(技術分野)
本考案は、搭載部品の位置出しが簡単で且つ発
熱を軽減する配線構造を有した混成集積回路に関
する。[Detailed Description of the Invention] (Technical Field) The present invention relates to a hybrid integrated circuit having a wiring structure that allows easy positioning of mounted components and reduces heat generation.
(従来技術)
パワートランジスタチツプの如きパワー回路部
を備えた混成集積回路を参考に当該回路の問題点
を説明する。第1図はパワー回路部を含む回路の
概略図であり、1はアース端子、2は電源端子で
あり、入力端子3と出力端子4との間に制御回路
部5とパワー回路部6が縦続的に接続される。制
御回路部5では、その入力信号に基づいて所要の
制御信号が出力され、パワー回路部6はこの制御
信号に基づいて駆動信号を出力端子4に出力す
る。通常、出力端子4にはソレノイド、ランプ等
の負荷が接続され、所要の駆動電流がこれらの負
荷に供給される。(Prior Art) The problems of a hybrid integrated circuit including a power circuit section such as a power transistor chip will be explained with reference to the circuit. FIG. 1 is a schematic diagram of a circuit including a power circuit section, where 1 is a ground terminal, 2 is a power terminal, and a control circuit section 5 and a power circuit section 6 are connected in series between an input terminal 3 and an output terminal 4. connected. The control circuit section 5 outputs a required control signal based on the input signal, and the power circuit section 6 outputs a drive signal to the output terminal 4 based on this control signal. Usually, a load such as a solenoid or a lamp is connected to the output terminal 4, and a required drive current is supplied to these loads.
第2図、第3図は上記回路を混成集積回路で構
成した従来例を示す。第2は平面図、第3図は第
2図中のA−A線断面図である。本図において、
5は制御回路部で、6はパワー回路部である。パ
ワー回路部6では、放熱板7の上に半田層8を介
してセラミツク基板9を設け、この上にパワー回
路部を構成している。先ずセラミツク基板9上に
例えばAg−Pdから成る印刷焼成導体10と半田
層11を介してヒートシンク12とボンデイング
ポスト13を載置している。ヒートシンク12は
パワートランジスタチツプ14の放熱導体をな
し、ボンデイングポスト13はパワートランジス
タのコレクタ電極を取出すために用いられるもの
である。そして上記印刷半田層11を形成する前
の段階において、上記ボンデイングポスト13を
位置決めするためのオーバーガラス15を印刷焼
成している。上記ヒートシンク12の上には高温
半田層16を介してパワートランジスタチツプ1
4が載置され、このパワートランジスタチツプ1
4のエミツタとベースが、制御回路部5とアルミ
ワイヤ線17,17で結線される。一方ボンデイ
ングポスト13も制御回路部5とアルミワイヤ線
17で結線される。 FIGS. 2 and 3 show conventional examples in which the above circuit is constructed from a hybrid integrated circuit. The second is a plan view, and FIG. 3 is a sectional view taken along the line A--A in FIG. In this figure,
5 is a control circuit section, and 6 is a power circuit section. In the power circuit section 6, a ceramic substrate 9 is provided on a heat sink 7 with a solder layer 8 interposed therebetween, and the power circuit section is constructed on this. First, a heat sink 12 and a bonding post 13 are placed on a ceramic substrate 9 via a printed and fired conductor 10 made of, for example, Ag--Pd and a solder layer 11. The heat sink 12 serves as a heat dissipation conductor for the power transistor chip 14, and the bonding post 13 is used to take out the collector electrode of the power transistor. Before forming the printed solder layer 11, an over glass 15 for positioning the bonding post 13 is printed and fired. A power transistor chip 1 is placed on the heat sink 12 via a high temperature solder layer 16.
4 is mounted, and this power transistor chip 1
The emitter and base of No. 4 are connected to the control circuit section 5 with aluminum wires 17, 17. On the other hand, the bonding post 13 is also connected to the control circuit section 5 with an aluminum wire 17.
以上において、前記パワー回路部6では第3図
中破線I1に示す如く電流が流れる。このため印刷
焼成導体10には大電流が流れ、この導体のパタ
ーン幅を電流量に応じて広げる必要がある。更に
は、ボンデイングポスト13の位置決めをするた
めにオーバーガラス15を印刷焼成する必要があ
るためパワー回路部6のコストが上昇するという
欠点を有していた。加えて、印刷焼成導体10に
Ag−Pdを使用する場合には導体抵抗が大きくな
るので、出力端子側からみたときパワートランジ
スタの飽和電圧が上記導体抵抗による電圧降下分
だけ大きくなり、このため混成集積回路の発熱量
が大きくなるという欠点を有していた。 In the above, a current flows in the power circuit section 6 as shown by the broken line I1 in FIG. Therefore, a large current flows through the printed and fired conductor 10, and it is necessary to widen the pattern width of this conductor in accordance with the amount of current. Furthermore, since it is necessary to print and bake the over glass 15 in order to position the bonding post 13, there is a drawback that the cost of the power circuit section 6 increases. In addition, the printed fired conductor 10
When using Ag-Pd, the conductor resistance increases, so when viewed from the output terminal side, the saturation voltage of the power transistor increases by the voltage drop due to the conductor resistance, which increases the amount of heat generated by the hybrid integrated circuit. It had the following drawback.
(考案の目的)
本考案は、上記諸問題を解決すべく成されたも
ので、パワー回路部等における通電用の印刷焼成
導体の配線パターン幅を電流量に関係なくほぼ一
定に保ち、この印刷焼成導体の形成によつて電極
を取り付ける際にその位置決めを容易に行い、且
つ上記印刷焼成導体の抵抗値を小さくせしめて発
熱を軽減することを目的とする。(Purpose of the invention) The present invention was made to solve the above-mentioned problems, and the width of the wiring pattern of the printed fired conductor for carrying electricity in the power circuit section etc. is kept almost constant regardless of the amount of current, and the printed It is an object of the present invention to facilitate positioning of electrodes when attaching them by forming a fired conductor, and to reduce heat generation by reducing the resistance value of the printed fired conductor.
(考案の構成)
本考案に係る混成集積回路は、複数の載置ラン
ドおよびこれらの載置ランド間の配線部を印刷焼
成導体で形成し、各載置ランドにボンデイングポ
スト等の単一電極部品および回路部品を半田付け
によつて固設した混成集積回路において、単一電
極部品を固設する載置ランドの形状を単一電極部
品の端面形状と略同形状をし、この載置ランドと
の間に少なくとも2つの配線部を対象的な位置関
係となるよう、また、その配線部は単一電極部品
を固設する載置ランド中心から放射状に出てかつ
その隣同士の配線部の成す角度が等しくなるよう
形成するとともに、この載置ランドおよびこれら
の配線部上にリフロー炉で溶融した後に単一電極
部品を固設するための印刷半田を塗布したことを
特徴とする。(Structure of the invention) The hybrid integrated circuit according to the invention includes a plurality of mounting lands and wiring sections between these mounting lands made of printed and fired conductors, and a single electrode component such as a bonding post on each mounting land. In a hybrid integrated circuit in which circuit components are fixed by soldering, the mounting land on which the single electrode component is fixed has approximately the same shape as the end face shape of the single electrode component, and At least two wiring parts should be placed in a symmetrical positional relationship between the wiring parts, and the wiring parts should be arranged radially from the center of the mounting land on which the single electrode component is fixed, and the wiring parts formed by the adjacent wiring parts. They are formed so that the angles are equal, and printed solder for fixing the single electrode component is applied onto the mounting land and these wiring parts after being melted in a reflow oven.
(実施例)
以下に本考案の好適一実施例を添付図面に基づ
いて説明する。(Embodiment) A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.
第4図は本考案に係る混成集積回路の平面図、
第5図は第4図中B−B線断面図である。 FIG. 4 is a plan view of a hybrid integrated circuit according to the present invention;
FIG. 5 is a sectional view taken along the line BB in FIG. 4.
18は放熱板であり、例えばニツケルメツキさ
れた銅板によつて形成される。この放熱板18の
上面には半田層19を印刷し、更に半田層19の
上にセラミツク基板20を設けている。セラミツ
ク基板20の上には、所定の形状を有する厚さ
20μの印刷焼成導体21が形成される。この印刷
焼成導体21には例えばAg−Pdが使用される。
印刷焼成導体21の平面形状は第6図に示す通り
で、パワートランジスタチツプを載置するランド
21aと、コレクタ用ボンデイングポストを載置
するランド21bとを有して成り、この21aと
21bの間は対称的な位置にある2本の配線部2
1c,21cによつて分割状態で接続されてい
る。上記ランド21aには、厚さ200μの半田層
22を介して厚さ1mmの銅板から成るヒートシン
ク23が設けられ、更にヒートシンク23上に印
刷又は塗布により高温半田層24を介しパワート
ランジスタチツプ25が載置されている。一方、
上記ランド21bには、上記と同様な半田層26
を介してボンデイングポスト27を取り付ける。
このボンデイングポスト27はコレクタ電極を成
す。この場合においてボンデイングポスト27の
半田付ランド21bはボンデイングポストの断面
形状と同一形状で且つ0.5〜1mm程度直径が大き
くなつている。このようにしてパワー回路部6が
形成される。 Reference numeral 18 denotes a heat sink, which is made of, for example, a nickel-plated copper plate. A solder layer 19 is printed on the upper surface of this heat sink 18, and a ceramic substrate 20 is further provided on the solder layer 19. On the ceramic substrate 20, a thickness having a predetermined shape is formed.
A printed fired conductor 21 of 20μ is formed. For example, Ag-Pd is used for this printed and fired conductor 21.
The planar shape of the printed and fired conductor 21 is as shown in FIG. 6, and consists of a land 21a on which a power transistor chip is placed and a land 21b on which a collector bonding post is placed, and between these 21a and 21b. are the two wiring sections 2 in symmetrical positions.
1c and 21c in a divided state. A heat sink 23 made of a 1 mm thick copper plate is provided on the land 21a via a 200 μ thick solder layer 22, and a power transistor chip 25 is mounted on the heat sink 23 via a high temperature solder layer 24 by printing or coating. It is placed. on the other hand,
The land 21b has a solder layer 26 similar to that described above.
Attach the bonding post 27 via the.
This bonding post 27 constitutes a collector electrode. In this case, the soldering land 21b of the bonding post 27 has the same cross-sectional shape as the bonding post, and has a larger diameter by about 0.5 to 1 mm. In this way, the power circuit section 6 is formed.
次いでその製造手順を述べると、先ず、高温半
田層24を載せたヒートシンク23の上にパワー
トランジスタチツプ25を載せ、これを高温リフ
ロー炉に通すことにより一体化する。その後、該
ヒートシンク23とボンデイングポスト27を、
印刷焼成導体21と半田層22,26を有するセ
ラミツク基板20に載せ、再びリフロー炉に通す
ことによりこれを一体化する。更に、前記一体物
を半田層19を介して放熱板18上に載せ、リフ
ロー炉に通す。こうして混成集積回路のパワー回
路部が形成される。 Next, the manufacturing procedure will be described. First, the power transistor chip 25 is placed on the heat sink 23 on which the high-temperature solder layer 24 is placed, and the chip is integrated by passing it through a high-temperature reflow oven. After that, the heat sink 23 and the bonding post 27 are
It is placed on a ceramic substrate 20 having a printed fired conductor 21 and solder layers 22 and 26, and is integrated by passing it through a reflow oven again. Further, the integrated product is placed on the heat sink 18 via the solder layer 19, and passed through a reflow oven. In this way, the power circuit portion of the hybrid integrated circuit is formed.
他方、放熱板18上の他の部分には、接着剤に
よつて、各種制御素子・部品が半田付けにより設
けられた制御部セラミツク基板28を固設する。
そして前記パワートランジスタチツプ25のエミ
ツタ、ベースの各電極及びコレクタ用ボンデイン
グポスト27と制御回路部の各ボンデイングポス
ト29……との間には例えば直径0.3mmのアルミ
ワイヤ30,31,32が接続される。 On the other hand, on the other part of the heat sink 18, a controller ceramic substrate 28, on which various control elements and parts are soldered, is fixed with adhesive.
For example, aluminum wires 30, 31, 32 with a diameter of 0.3 mm are connected between the emitter, base electrodes and collector bonding posts 27 of the power transistor chip 25 and the bonding posts 29 of the control circuit section. Ru.
以上において、上記混成集積回路のパワー回路
部6では、破線I2で示す如く、コレクタ用アルミ
ワイヤ32→ボンデイングポスト27→印刷焼成
導体21及び印刷半田層22,26→ヒートシン
ク23→高温半田層24→パワートランジスタチ
ツプ25のエミツタ→エミツタ用アルミワイヤ3
0と電流が流れる。斯かる電流ルートI2におい
て、第6図に示すようにボンデイングポスト27
とヒートシンク23との間の配線を、それぞれボ
ンデイングポスト27、ヒートシンク23を載置
せしめるランド21b,21aと、これらを結び
軸線Cについて線対称に分割された2本の配線部
21c,21cとから成る印刷焼成導体21によ
つて形成した。これによつて電流ルートI2を流れ
る電流は、配線部21c,21cにおいて分流し
つつ、印刷焼成導体21及び半田層22,26に
流れることになる。 In the above, in the power circuit section 6 of the hybrid integrated circuit, as shown by the broken line I2 , collector aluminum wire 32 → bonding post 27 → printed fired conductor 21 and printed solder layers 22, 26 → heat sink 23 → high temperature solder layer 24 → Emitter of power transistor chip 25 → Aluminum wire for emitter 3
0 and current flows. In such current route I2 , bonding post 27 is connected as shown in FIG.
The wiring between the bonding post 27 and the heat sink 23 consists of lands 21b and 21a on which the bonding post 27 and the heat sink 23 are placed, respectively, and two wiring parts 21c and 21c that connect these and are divided symmetrically about the axis C. It was formed by a printed fired conductor 21. As a result, the current flowing through the current route I 2 flows through the printed and fired conductor 21 and the solder layers 22 and 26 while being divided at the wiring portions 21c and 21c.
上記において、配線部21c,21cの幅はボ
ンデイングポスト27の直径よりも小さくなつて
いる。上記の如くボンデイングポスト27とヒー
トシンク23との間の配線を2分割とし、印刷焼
成導体21の上に印刷半田層22,26を形成す
るようにしたため、配線部の幅を小さくすること
ができると共に通電部全体としての抵抗を小さく
することができる。またボンデイングポスト27
を載置せしめる導体部分21bにおいて、反対方
向に対称的に配線部21c,21cを引き出すよ
うにしたため、半田層26の溶融時にその表面張
力を均等に割り振ることができ、これによりボン
デイングポスト27の位置決めを正確に行うこと
ができる。 In the above, the width of the wiring portions 21c, 21c is smaller than the diameter of the bonding post 27. As described above, the wiring between the bonding post 27 and the heat sink 23 is divided into two parts, and the printed solder layers 22 and 26 are formed on the printed fired conductor 21, so that the width of the wiring part can be reduced and The resistance of the current-carrying section as a whole can be reduced. Also bonding post 27
In the conductor portion 21b on which the bonding post 27 is placed, the wiring portions 21c, 21c are pulled out symmetrically in opposite directions, so that the surface tension of the solder layer 26 can be evenly distributed when it is melted. can be done accurately.
第7図は本考案の第2実施例を示す。本実施例
においては、印刷焼成導体33におけるヒートシ
ンク23を載置せしめるランド33aとボンデイ
ングポスト27を載置せしめるランド33bとの
間を、四方向に放射状に引き出された対称的位置
にある配線部33c……で接続する。斯かる配線
構造によつて、前記と同様な作用によりボンデイ
ングポスト27の位置決めを正確に行えるように
するとともに、ボンイングポスト27とパワート
ランジスタチツプ25との間の通電部の抵抗を小
さくすることができる。 FIG. 7 shows a second embodiment of the invention. In this embodiment, wiring portions 33c are symmetrically drawn out in four directions between a land 33a on which the heat sink 23 is placed on the printed fired conductor 33 and a land 33b on which the bonding post 27 is placed. Connect with... With such a wiring structure, the bonding post 27 can be accurately positioned by the same effect as described above, and the resistance of the current-carrying portion between the bonding post 27 and the power transistor chip 25 can be reduced. can.
なお上記配線部の本数は更に増加することもで
きる。 Note that the number of the above-mentioned wiring portions can also be further increased.
前記本考案に係る混成集積回路のパワー回路部
の配線構造は、パワー回路部品に限らず、小信号
回路部品の搭載位置出しの方法としても適用する
ことができる。 The wiring structure of the power circuit section of the hybrid integrated circuit according to the present invention can be applied not only to power circuit components but also as a method for locating small signal circuit components.
(考案の効果)
以上の説明で明らかなように本考案によれば、
印刷焼成導体によつて形成された配線部の形状そ
のものによつて載置部品の位置決めを簡単に行う
ことができるので従来の位置決め用部品の削減、
製造工程の簡略化を達成することができる。また
配線部を含む通電部分の抵抗を小さくすることが
できるため全体の発熱量を減少することができる
等の諸特長を発揮する。(Effect of the invention) As is clear from the above explanation, according to the invention,
The positioning of the mounted components can be easily performed by the shape of the wiring part formed by the printed and fired conductor, which reduces the need for conventional positioning components.
Simplification of the manufacturing process can be achieved. Furthermore, since the resistance of current-carrying parts including wiring parts can be reduced, the overall heat generation amount can be reduced.
第1図はパワー回路等を含む回路の概略図、第
2図は第1図の回路を実現する従来の混成集積回
路の平面図、第3図は第2図中のA−A線断面
図、第4図は本考案に係る混成集積回路の平面
図、第5図は第4図中のB−B線断面図、第6図
は印刷焼成導体の形状を示す図、第7図は本考案
の第2実施例に係る第6図と同様な図である。
5……制御回路部、6……パワー回路部、7,
18……放熱板、8,10,11,16,19,
22,24,26……半田、9,20……セラミ
ツク基板、10,21,33……印刷焼成導体、
12,23……ヒートシンク、13,27……ボ
ンデイグポスト、14,25……パワートランジ
スタチツプ、21a,21b,33a,33b…
…ランド、21c,33c……配線部。
Figure 1 is a schematic diagram of a circuit including a power circuit, etc., Figure 2 is a plan view of a conventional hybrid integrated circuit that realizes the circuit in Figure 1, and Figure 3 is a cross-sectional view taken along line A-A in Figure 2. , FIG. 4 is a plan view of the hybrid integrated circuit according to the present invention, FIG. 5 is a sectional view taken along line B-B in FIG. 4, FIG. 6 is a diagram showing the shape of the printed and fired conductor, and FIG. 7 is a diagram similar to FIG. 6 according to a second embodiment of the invention; FIG. 5... Control circuit section, 6... Power circuit section, 7,
18... Heat sink, 8, 10, 11, 16, 19,
22, 24, 26... Solder, 9, 20... Ceramic substrate, 10, 21, 33... Printed fired conductor,
12, 23... Heat sink, 13, 27... Bonding post, 14, 25... Power transistor chip, 21a, 21b, 33a, 33b...
...Land, 21c, 33c...Wiring section.
Claims (1)
の配線部を印刷焼成導体で形成し、前記各載置ラ
ンドにボンデイングポスト等の単一電極部品およ
び回路部品を半田付けによつて固設した混成集積
回路において、前記単一電極部品を固設する載置
ランドの形状を前記単一電極部品の端面形状と略
同形状をし、この載置ランドとの間に少なくとも
2つの配線部を対象的な位置関係となるよう、ま
た、その配線部は前記単一電極部品を固設する載
置ランド中心から放射状に出てかつその隣同士の
配線部の成す角度が等しくなるよう形成するとと
もに、この載置ランドおよびこれらの配線部上に
リフロー炉で溶融した後に前記単一電極部品を固
設するための印刷半田を塗布したことを特徴とす
る混成集積回路。 A hybrid structure in which multiple mounting lands and the wiring between these mounting lands are formed of printed and fired conductors, and single electrode parts such as bonding posts and circuit components are fixed to each of the mounting lands by soldering. In the integrated circuit, the shape of the mounting land on which the single electrode component is fixedly mounted is substantially the same as the end face shape of the single electrode component, and at least two wiring portions are symmetrically arranged between the mounting land and the mounting land. In addition, the wiring portions are formed so as to radiate out from the center of the mounting land on which the single electrode component is fixed, and the angles formed by adjacent wiring portions are equal. 1. A hybrid integrated circuit characterized in that a printed solder for fixing the single electrode component is applied onto the mounting land and the wiring portion thereof after being melted in a reflow oven.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984062036U JPS60174255U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984062036U JPS60174255U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60174255U JPS60174255U (en) | 1985-11-19 |
| JPH0442943Y2 true JPH0442943Y2 (en) | 1992-10-12 |
Family
ID=30590864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984062036U Granted JPS60174255U (en) | 1984-04-25 | 1984-04-25 | hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60174255U (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5526638A (en) * | 1978-08-16 | 1980-02-26 | Hitachi Ltd | Water cooled type cooling device for transformer |
-
1984
- 1984-04-25 JP JP1984062036U patent/JPS60174255U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60174255U (en) | 1985-11-19 |
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