JPH0443036U

JPH0443036U -

Info

Publication number: JPH0443036U
Application number: JP8531490U
Authority: JP
Priority date: 1990-08-09
Filing date: 1990-08-09
Publication date: 1992-04-13

Description

[Brief explanation of the drawing]

第１図は、本考案の携帯用無線電話のブロツク
図、第２図は、同じく通信制御回路のブロツク図
である。３……通信制御回路、３Ａ……受信データ用デ
イジタルＰＬＬ回路、３Ｃ……ＳＡＴ用デイジタ
ルＰＬＬ回路、３Ｅ……待ち受け制御回路。 FIG. 1 is a block diagram of a portable radio telephone according to the present invention, and FIG. 2 is a block diagram of a communication control circuit. 3... Communication control circuit, 3A... Digital PLL circuit for received data, 3C... Digital PLL circuit for SAT, 3E... Standby control circuit.

Claims

[Scope of utility model registration request]

In a device that receives a data signal and a SAT (Supervisor Audio Tone) signal transmitted at a predetermined word rate and bit rate, a first PLL circuit generates a data clock signal synchronized with the data signal, and a first PLL circuit synchronized with the SAT signal. a second PLL circuit that generates a return signal, a clock circuit that supplies a clock signal to each of the PLL circuits, and control means that cuts off the supply of the clock signal to the second PLL circuit during standby. portable wireless communication device.