JPH0443069U - - Google Patents
Info
- Publication number
- JPH0443069U JPH0443069U JP8481790U JP8481790U JPH0443069U JP H0443069 U JPH0443069 U JP H0443069U JP 8481790 U JP8481790 U JP 8481790U JP 8481790 U JP8481790 U JP 8481790U JP H0443069 U JPH0443069 U JP H0443069U
- Authority
- JP
- Japan
- Prior art keywords
- output
- video signal
- level
- clamp circuit
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000007665 sagging Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案の一実施例を示すシエージング
補正等映像信号のペデスタルレベル変動自動検出
補正回路のブロツク図、第２図は同第１図の動作
波形図である。
１はペデスタルレベルのクランプ回路、２は映
像信号変調用乗算器、３はコンパレータ、６はバ
ツフアアンプである。
FIG. 1 is a block diagram of a circuit for automatically detecting and correcting pedestal level fluctuations in a video signal such as sagging correction, showing an embodiment of the present invention, and FIG. 2 is an operational waveform diagram of FIG. 1. 1 is a pedestal level clamp circuit, 2 is a video signal modulation multiplier, 3 is a comparator, and 6 is a buffer amplifier.
Claims (1)
接続し、同クランプ回路出力映像信号と同映像信
号変調用信号とをそれぞれ差動入力の乗算器に接
続し、同乗算器出力映像信号をラツチパルスのタ
イミングでペデスタルレベルをサンプリングして
基準電圧と比較する正負値出力のコンパレータに
接続し、同コンパレータ出力を低域通過フイルタ
を介してバツフアアンプに接続し、導バツフアア
ンプ出力を前記クランプ回路にフイードバツクし
てなる前記乗算器出力映像信号の直流レベルの変
動を自動補正をすることを特徴とする受像機。 Connect the video signal to a clamp circuit at the pedestal level, connect the video signal output from the clamp circuit and the signal for modulating the video signal to a differential input multiplier, and output the video signal from the multiplier to the pedestal level at the timing of the latch pulse. The multiplier is connected to a comparator with a positive/negative output that samples the level and compares it with a reference voltage, the output of the comparator is connected to a buffer amplifier via a low-pass filter, and the output of the buffer amplifier is fed back to the clamp circuit. A television receiver characterized by automatically correcting fluctuations in the DC level of an output video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8481790U JPH0443069U (en) | 1990-08-10 | 1990-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8481790U JPH0443069U (en) | 1990-08-10 | 1990-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0443069U true JPH0443069U (en) | 1992-04-13 |
Family
ID=31633548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8481790U Pending JPH0443069U (en) | 1990-08-10 | 1990-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0443069U (en) |
-
1990
- 1990-08-10 JP JP8481790U patent/JPH0443069U/ja active Pending
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