JPH0443260U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a flaw detection device according to an embodiment of the invention, Fig. 2 is a waveform diagram in which noise is superimposed on the defect reflected wave of the flaw detection signal, and Fig. 3 is a reference voltage setting diagram of a comparator. FIG. 4 is a timing diagram of a flaw detection signal, and FIG. 5 is a timing diagram according to an embodiment of the present invention.

Claims (1)

[Scope of utility model registration request] After the signal output detected as the reflected wave of the ultrasonic pulse is half-wave or full-wave rectified by a detection circuit, it is supplied to multiple gate circuits divided into ranges corresponding to the inspection area of the target object, and each gate A comparator with multiple different reference voltages is provided for each circuit, and a counter is provided to count the number of times the signal exceeds the reference voltage by passing it through a gate circuit at each repetition frequency. By outputting a defect signal under the condition that the number of times counted becomes large, it is possible to distinguish between noise and defects.The output of the comparator is input to a weighting circuit, and the size of the defect can be counted again. An ultrasonic flaw detection device characterized in that the length of a defect is supplied to a recording device using a one-shot circuit and a hold circuit that extend the defect signal for a time proportional to a set number of times N, and only the defect signal is output.