JPH044343U - - Google Patents

Info

Publication number
JPH044343U
JPH044343U JP4500090U JP4500090U JPH044343U JP H044343 U JPH044343 U JP H044343U JP 4500090 U JP4500090 U JP 4500090U JP 4500090 U JP4500090 U JP 4500090U JP H044343 U JPH044343 U JP H044343U
Authority
JP
Japan
Prior art keywords
simulating
microprocessor
section
peripheral
verifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4500090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4500090U priority Critical patent/JPH044343U/ja
Publication of JPH044343U publication Critical patent/JPH044343U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係る構成を示すブ
ロツク図、第2図は本考案の一実施例に係る具体
的な構成を示すブロツク図、第3図は従来例を示
すブロツク図である。 11,21…環境設定部、12,22…入出力
部、13…メモリシミユレート部、14,24…
CPUシミユレート部、15,25…下界シミユ
レート部、16,26…周辺ICシミユレート部
FIG. 1 is a block diagram showing a configuration according to an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration according to an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example. be. 11, 21... Environment setting section, 12, 22... Input/output section, 13... Memory simulation section, 14, 24...
CPU simulating section, 15, 25... lower bound simulating section, 16, 26... peripheral IC simulating section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロプロセツサのCPU動作をシミユレー
トすることによりプログラムの検証を行なう装置
に於いて周辺IC動作をシミユレートする部分を
設けてなることを特徴とするマイクロプロセツサ
シミユレータ。
1. A microprocessor simulator comprising a device for verifying a program by simulating the CPU operation of a microprocessor, and further comprising a part for simulating peripheral IC operation.
JP4500090U 1990-04-26 1990-04-26 Pending JPH044343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4500090U JPH044343U (en) 1990-04-26 1990-04-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4500090U JPH044343U (en) 1990-04-26 1990-04-26

Publications (1)

Publication Number Publication Date
JPH044343U true JPH044343U (en) 1992-01-16

Family

ID=31558798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4500090U Pending JPH044343U (en) 1990-04-26 1990-04-26

Country Status (1)

Country Link
JP (1) JPH044343U (en)

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