JPH0443674A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE:To realize the higher integration and the larger capacity of a semiconductor memory device by a method wherein a diffusion layer is formed inside a well region, a first conductive layer which is connected electrically to the diffusion layer is formed, a titanium nitride film and a tantalum oxide film are formed on it and a second conductive layer is formed. CONSTITUTION:A P-type well 2 is formed on a silicon substrate 1; an isolation oxide film 3 and, in addition, a transistor 4 for memory-cell selection use are formed on the well; an N-type diffusion layer 5 is formed in a source region and a drain region; an oxide film 6 is deposited; a contact window is opened in a prescribed part of the oxide film 6 on the N-type diffusion layer 5 in the source region of the selection transistor 4; a polycrystalline silicon electrode 7 to be used as a capacity electrode is formed. In succession, a titanium nitride (TiN) film 8 is formed; a tantalum oxide (Ta2O5) film 9 is deposited; a tungsten electrode 10 as another cell capacity electrode is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same.

BACKGROUND OF THE INVENTION In recent years, as DRAMs have become more highly integrated and have larger capacities, it has become essential to have highly integrated memory cells, which occupy about half of the chip size. Due to the demand for miniaturization of these memory cells, it is necessary to ensure reliability as memory cells.

In order to satisfy the requirement of having sufficient cell capacitance (40 fF or more) as part of ensuring reliability, the structure of the cell capacitor element is a grooved capacitor with a three-dimensional structure, instead of a conventional flat plate capacitor. Laminated structure capacitance etc. have been proposed.

FIG. 3 is a cross-sectional view of a capacitive portion of a memory cell having a three-dimensional stacked structure.

In FIG. 3, 1 is a P-type silicon substrate, 2 is a P-type well region, 3 is an isolation oxide film, 4 is a selection transistor, 5 is an N-type diffusion layer, 6 is a silicon oxide film, 7 is a polycrystalline silicon electrode, 11 is a silicon oxide/silicon nitride/silicon oxide laminated insulating film, and 12 is a polycrystalline silicon electrode.

A polycrystalline silicon oxide film 6 formed on a silicon substrate 1 having an N-type diffusion layer 5 of the same or opposite conductivity type as the P-type silicon substrate 1 is electrically connected to the N-type diffusion layer 5 at a predetermined portion of the silicon oxide film 6. After forming the silicon film, the polycrystalline silicon film is processed using known photolithography and dry etching techniques to form a polycrystalline silicon electrode 7 that will serve as the lower electrode of the capacitor. Next, a thin silicon oxide film is formed on the surface of the polycrystalline silicon electrode 7. Thereafter, a silicon nitride film is deposited on the very thin silicon oxide film, and the surface of the silicon nitride film is thermally oxidized to form a silicon oxide film. In this way, the silicon oxide film/silicon nitride film/silicon oxide film laminated insulating film 11 is formed. Thereafter, by depositing a polycrystalline silicon electrode 12 that becomes the upper electrode of the capacitor, a single conductor capacitor is formed in which the polycrystalline silicon is used as the electrode and the laminated insulating film 11 made of the silicon nitride film and the silicon oxide film is used as the insulating film. . In the capacitive element of this structure, capacitance is also formed in the side wall portion of the polycrystalline silicon electrode 7, which is the electrode, and the insulating film is a laminated insulating film 11 of a silicon oxide film and a silicon nitride film, so compared to a single oxidized Schifcon film. It has a high dielectric constant and can secure a larger capacitance than a flat plate capacitor.

Problems to be Solved by the Invention In a capacitive element whose insulating film has a three-dimensional laminated structure, the side wall portion of the polycrystalline silicon film that is the electrode can also be used as a capacitor. Therefore, compared to a flat plate type capacitor, a larger capacity can be secured with the same occupied area.

In particular, large capacitance can be secured by forming the lower electrode on an insulating film with a large surface irregularity, or by arranging the lower electrode and the upper electrode alternately in a comb shape to form a multilayered structure. I can do it. As the capacitive insulating film, a silicon oxide film or a stacked insulating film 11 of a silicon oxide film and a silicon nitride film is used.

However, the dielectric constant of a silicon oxide film is 3.9, and even a silicon nitride film, which has a higher dielectric constant than a silicon oxide film, has a dielectric constant of only 7.0. However, a dielectric constant of only about 5 to 6 can be obtained. Therefore, no matter how much a trench structure, stack structure, or composite structure of trenches and stacks is used, there is a limit to further increase in memory cell capacity. In other words, as memory cells become further miniaturized, a shortage of cell capacity occurs. Therefore, in recent years, tantalum oxide films (Ta205) having a high dielectric constant have been studied in place of these silicon oxide films and silicon nitride films. Since tantalum oxide film has a high dielectric constant of 20 to 28, it achieves cell capacity 5 to 7 times that of silicon oxide film and 3 to 4 times that of silicon nitride film with the same film thickness and electrode area. can do. Therefore, if the cell capacity to be secured is the same as the conventional one, the cell area can be reduced to 1/3 to 1/7. However, when a tantalum oxide film is actually formed on a polycrystalline silicon film and a single crystal silicon film, a 1 to 2 nm thick Schifcon oxide film grows on the polycrystalline silicon film and single crystal silicon film due to natural oxidation. do. Therefore, even if a tantalum oxide film with a high dielectric constant is formed on top of this, it will become a composite film of a natural oxide film and a tantalum oxide film, and its dielectric constant will be 1/3 to 1/3 that of a single layer tantalum oxide film.
/4. This phenomenon occurs similarly even when a composite film of a silicon nitride film and a tantalum oxide film is used as a capacitor insulating film, and the effective film thickness becomes thick due to the presence of the natural oxide film, making it impossible to ensure sufficient cell capacity. In addition, this natural oxide film can be removed by a known etching method,
Furthermore, even if the polycrystalline silicon film and the m-crystalline silicon film are handled using known techniques to prevent the growth of a natural oxide film, and a clean silicon surface with no natural oxide film is obtained, the tantalum oxide film will not form with silicon. It has high reactivity (easily reduced to tantalum metal by heat treatment. This causes leakage current and dielectric constant to increase (loss) as a fully stranded film.

The present invention is intended to solve the above-mentioned shortage of cell capacity, and while it has the high dielectric constant of tantalum oxide film as a capacitive insulating film, it is also possible to reduce the dielectric constant due to the capacitive electrode and the anxiety of the tantalum oxide film. It is an object of the present invention to provide a method for manufacturing a semiconductor memory device having a structure that suppresses cell capacity and further increases cell capacity.

Means for Solving the Problems The method for manufacturing a semiconductor memory device of the present invention provides a method for manufacturing a semiconductor memory device of the present invention, in which a well region having the same conductivity type as the substrate formed on a silicon substrate of one conductivity type has a conductivity type opposite to that of the well. a step of forming a conductive type diffusion layer; a step of forming a conductive polycrystalline silicon film as a first conductive layer that is electrically connected to the diffusion layer and constitutes one of the memory cell capacitances; A step of forming a titanium nitride film on polycrystalline silicon, which is a conductive layer, a step of forming a tantalum oxide film as a capacitor insulating film on the titanium nitride film, and a step of forming a cell capacitor on the tantalum oxide film. The method includes a step of forming a second conductive layer.

Function: According to the memory cell structure formed by this manufacturing method, due to the presence of the titanium nitride film, which is a transparent conductive layer formed on the polycrystalline silicon film, the cell capacity is influenced by the natural oxide film on the polycrystalline silicon film. In addition, the titanium nitride film acts as a barrier to the reaction between the tantalum oxide film, which is a capacitor insulating film, and the polycrystalline silicon film. As a result, if the required memory cell capacity is the same as the conventional structure, and the tantalum oxide film is the same thickness as the conventional structure, the oxidation 11 when using a silicon film as a capacitive insulating film
It is possible to realize a memory cell having a cell area of 5 to 1/7, and 1/4 to 115 of that of a composite film of a silicon oxide film and a silicon nitride film.

Embodiments Specific embodiments of the present invention will be explained using the drawings. 1st
The figure shows a first embodiment of a stacked capacitor cell in which a conductive polycrystalline silicon film is used as one of the cell capacitor electrodes as an embodiment of the present invention. A p-type (100) surface, a silicon substrate 1 with a specific resistance of 5 to 20 ΩcI11 is coated with a depth of 3-2 μm % average concentration 3X by a known selective diffusion technique.
A P-type well 2 of 1016/c- is formed, and an isolation oxide film 3 and a memory cell selection transistor 4 are formed in advance on this well by a known selective oxidation method.

This selection transistor 4 has been previously channel doped for threshold voltage control. The structure of the transistor is a lightly doped drain (LDI) structure with sidewalls of a well-known oxide film, and an N-type diffusion layer 5 is formed in the source and drain regions (see Fig. 1(a)). )). After this, cell capacitance will be formed on the well and on the selection transistor 4, so
In order to electrically insulate the selection transistor 4 and the cell capacitor electrode, tetraethoxyorthosilane (TE0
Using 1) as a raw material, an oxide film 6 with a thickness of 110 mm is formed by the LPCVD method.
0n deposited. After that, i! A contact window is opened in a predetermined portion of the oxide film 6 on the N-type diffusion layer 5 in the source region of the selection transistor 4 to electrically connect the source portion of the selection transistor 4 to one of the cell capacitor electrodes. . After that, 3x phosphorus atoms were removed at 600°C by LPCVD method
300 nm thick polycrystalline silicon film containing 1020/cj
deposited and enhanced by known photolithography techniques.
Form a polycrystalline silicon electrode 7 that will become a t-pole (see Fig. 1 (
b)). Next, titanium (Tj) #40 was deposited using the CVD method.
After depositing 100 nm, titanium nitride (TiN) is formed by nitriding at 650°C for 20 seconds in a pure ammonia atmosphere using a rapid thermal process (RTP3 method) using an arc lamp as a heat source.Next, a known photolithography technique is used. Then, the titanium nitride film 8 is selectively etched using a selective etching technique, so that the titanium nitride film 8 covers the surface of the polycrystalline silicon electrode 7, which will become a capacitor electrode.Thereafter, Ta (N (CH, )2)
, a tantalum oxide (T a 206 ) film 9 is deposited to a thickness of 10 nm at 650° C. using gas and oxygen gas as raw materials (first step).
Figure (C)). Thereafter, a tungsten electrode 10 with a thickness of 200 nm was formed as the other electrode of the cell capacitance electrode by CVD method.
Then, electrodes are formed using a known dry etching technique to form a stacked memory cell (see Figure 1(d)).
)).

According to the memory cell structure formed using this manufacturing method, the cell capacitance is increased due to the presence of the titanium nitride film, which is a transparent conductive layer formed on the polycrystalline silicon film, and the influence of the natural oxide film on the polycrystalline silicon film is reduced. In addition, the titanium nitride film acts as a barrier to the reaction between the tantalum oxide film, which is a capacitor insulating film, and the polycrystalline silicon film. In this way, the high dielectric constant of 20 to 28, which is a characteristic of the tantalum oxide film, can be utilized. As a result, if the capacitance required as the memory cell capacitance is the same as that of the conventional structure, and the thickness of the tantalum oxide film is the same as that of the conventional structure, it is found that if the silicon oxide film is used as the capacitive insulating film,
It is possible to realize a memory cell having a cell area of 5 to 1/7, or 1/4 to 115 when using a composite film of a silicon oxide film and a silicon nitride film.

FIG. 2 shows a second embodiment of the invention in a plain capacitor cell in which a silicon substrate is used as the charge storage node of the cell capacitor.

A P-type well 2 with a depth of 3.2 μm is formed in a silicon substrate 1 having a P-type (100) plane and a resistivity of 5 to 20 ΩcIl+ using a known selective diffusion technique, and a well-known selective oxidation technique is used to form a P-type well 2 in this well region. An isolation oxide film 3 serving as an isolation region is formed. Next, an N-type diffusion layer 5 is formed in a predetermined portion of the P-type well 2, which is to become one electrode of the cell capacitance, by a known selective diffusion technique to form a capacitance electrode (Fig. 2(a)
)). Next, a titanium nitride film 8 is deposited to a thickness of 40 nm by reactive sputtering to cover the capacitive electrode of the N-type diffusion layer 5, and is etched into a predetermined shape slightly wider than the electrode area by a known etching technique (second Figure (b)).

Next, as a capacitive insulating film, tantalum oxide (Ta205
) Deposit film 9 to a thickness of 10 nm. Thereafter, as the other tungsten electrode 10 of the capacitor, tungsten is deposited to a thickness of 300 nm by sputtering (FIG. 2(C)), and the tungsten electrode 10/tantalum oxide film 9. /The titanium nitride film 8 is edged by a known dry etching technique to form a cell capacitance portion. After this step, a selection transistor 4 having a source electrically connected to one electrode of the cell capacitor made of the N-type diffusion layer 5 is formed, and the memory cell is completed (FIG. 2(d)).

According to the memory cell structure formed using this manufacturing method, the cell capacitance is increased due to the presence of the titanium nitride film, which is a transparent conductive layer formed on the polycrystalline silicon film, and the influence of the natural oxide film on the polycrystalline silicon film is reduced. In addition, the titanium nitride film acts as a barrier to the reaction between the tantalum oxide film, which is a capacitor insulating film, and the polycrystalline silicon film. In this way, the high dielectric constant of 20 to 28, which is a characteristic of the tantalum oxide film, can be utilized. As a result, if the capacitance required as the memory cell capacitance is the same as that of the conventional structure, and the thickness of the tantalum oxide film is the same as that of the conventional structure, it is found that if the silicon oxide film is used as the capacitive insulating film,
5 to 1, /7, it is possible to realize a memory cell with a cell area of 1/4 to 1.15 when using a composite film of a silicon oxide film and a silicon nitride film.

In the above embodiment, the Brenna structure was explained using a stacked capantor and a Brenna capacitor as an example, but a stacked trench 4 having a two-dimensional structure such as a trench
By applying the technology of the present invention to the Yabashita cell and the trend capacitor, it is possible to realize a memory cell with an even larger memory capacity.

Effects of the Invention As shown in F-F, according to the present invention, it is possible to realize a memory cell structure having an extremely large memory cell capacity, and it is possible to realize even higher integration and larger capacity of semiconductor memory devices. There is.

[Brief Description of the Drawings] Fig. 1 is a process sectional view showing the first embodiment of the present invention;
The figure is a process sectional view showing a second embodiment of the present invention, and FIG. 3 is a process sectional view showing a conventional example. 1... Silicon substrate, 2... P-type well, 3... Isolation oxide film, 4... Transistor, 5... N-type Diffusion layer, 6... Oxide film, 7... Polycrystalline silicon electrode, 8...
...Titanium nitride film, 9...Tantalum oxide film, 1
0...Tungsten electrode, ]1...Silicon oxide/silicon nitride/silicon oxide laminated insulating film,
12... Polycrystalline silicon electrode. Name of agent: Patent attorney Shigetaka Awano and one other person 1 Figure 2 Figure 11! Sour and January Dance Star Njik S, Slayer I/& Kajun Tata Ki Oto Todoroki Asoko J Sue fρ Tanges Nano Dentei

Claims (3)

[Claims] (1) A semiconductor substrate, a diffusion layer formed on the surface of the semiconductor substrate, a first conductive layer formed on the semiconductor substrate in contact with at least the diffusion layer, and a first conductive layer formed on the first conductive layer. 1. A semiconductor memory device comprising: a titanium nitride film, a tantalum oxide film formed on the titanium nitride film, and a second conductive layer formed at least on the tantalum oxide film. (2) The semiconductor memory device according to claim 1, wherein a plurality of tantalum oxide films, silicon nitride films, and tantalum oxide films are alternately stacked. (3) forming a diffusion layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of one conductivity type, forming an insulating film on the semiconductor substrate, and exposing at least a portion of the diffusion layer; forming a window by removing the insulating film, forming a first conductive layer connected to the diffusion layer through at least the window, and forming a titanium nitride film on the conductive layer. forming a tantalum oxide film on the titanium nitride film; and forming a second tantalum oxide film on the tantalum oxide film.
1. A method of manufacturing a semiconductor memory device, comprising: forming a conductive layer.