JPH0443832Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a watch with an alarm function that generates an alarm sound at a set time.

(Prior Art) Conventionally, as a method of more reliably waking up the user, it has been considered to control the alarm sound, especially the volume, according to the length of sleep, as shown in Japanese Patent Laid-Open No. 61-213788. There is. According to this, when you sleep for a long time, you can lower the volume, and when you sleep for a short time, you can increase the volume, so that you can wake up refreshed and reliably.

(Problem that the invention aims to solve) However, each person's sleeping time varies, and as in the past, the standard sleeping time is predetermined, and the difference between the standard sleeping time and the actual sleeping time causes the alarm sound to change. Controlling the volume may cause the alarm volume to be too loud or too low for some people, making it difficult to use.

(Means for Solving the Problems) In order to solve the above problems, the present invention is characterized in that the standard sleep time is the user's average sleep time. In order to calculate this average sleep time, the present invention uses a total sleep time counter that counts the total sleep time of a preset number of times, a shift register to divide the time by the set number of times, and a shift pulse generator. A circuit is installed. Further, before this average sleep time is calculated, an initial clear circuit and an initial value setting circuit are provided so that a set time is preset in the shift register instead of the average sleep time and compared with the actual sleep time.

(Embodiment) The drawing is a circuit diagram of an alarm clock according to an embodiment of the present invention.

The oscillation circuit 2 outputs a reference signal, and the frequency dividing circuit 4 divides the frequency of this reference signal. The time display section 6 displays the time based on the frequency-divided output signal from the frequency dividing circuit 4, and includes a waveform shaping circuit 8, a driver 10, a motor 12, and a wheel train 14.

The alarm circuit 16 includes a guide 18 built into the wheel train 14, an AND gate 22 into which a signal from the guide 18 and an operation signal from an alarm switch 20 are input, and an audible signal from the AND gate 22 and the frequency dividing circuit 4. and an AND gate 24 to which the frequency signal φ ₂ is input. Therefore, when the set time comes with the alarm switch 20 set, that is, turned on, and the output signal from the indicator 18 goes to H level, the AND gate 24 outputs the audible frequency signal φ ₂ as an alarm notification signal.

The sleep time counter 26 for counting the actual sleep time has a counter 28 and a clock input φ of this counter 28 for inputting the constant periodic signal φ ₁ from the frequency dividing circuit 4 only when the alarm switch 20 is on. and an inverter 32 and a one-shot multivibrator 34 connected between the reset input R of the counter 28 and the alarm switch 20.
Therefore, when the alarm switch 20 is turned on, the counter 28 starts counting the constant period signal φ ₁ from the frequency dividing circuit 2, and the alarm switch 20 is turned on.
By turning off 0, the count value is cleared by a single pulse from the one-shot multivibrator 34. In other words, the time from when the alarm is set until it stops sounding is counted as sleep time.

The constant periodic signal φ ₁ from the AND gate 30 is
It is also input to the clock input φ of the total sleep time counter 36. The carry output of the operation counter 40 via the delay circuit 38 is input to the reset input R of the total sleep time counter 36. This counter 40 is a quaternary counter, and the output of the one-shot multivibrator 34 is input to the clock input φ. This counter 40 increments the count every time the alarm switch 20 is turned off, and when the count value reaches "4", that is, the total sleep time for 4 days is counted in the total sleep time counter 36. is configured to clear its count value when

The count value of total sleep time counter 36 is provided to a data input of shift register 42 . The PE input of this shift register 42 has an OR gate 4.
4, the carry output of the operation counter 40 is directly input. Therefore, four days worth of sleep time is counted in the total sleep time counter 36, and immediately before this count value is cleared, the count value is preset in the shift register 42 by a carry output input to the PE input.

The output of the AND gate 48 of the shift pulse generating circuit 46 is input to the down clock input φ of the shift register 42. This and gate 4
8, constant period signal φ ₁ from frequency dividing circuit 4 and FF
The Q output signal of FF50 is inputted, and the set input S of FF50 receives a quaternary counter 40 via a delay circuit 38.
A carry signal from the counter 52 is input to the reset input R, and a carry signal from the counter 52 is input to the reset input R. This counter 52 is configured so that a carry signal is output when the count value reaches "2". The reset input R of this counter 52 has an FF
Therefore, the counter 52 is configured to start counting when the carry signal of the quaternary counter 40 is generated and to be reset at the same time as the carry signal is generated. The final count values of the counter 52 and the counter 40 have a relationship of " ⁿ " if the count value of the counter 40 is "2 n ", and n=2 in this embodiment. Further, a constant period signal φ ₁ from the frequency dividing circuit 4 similar to the AND gate 48 is input to the clock input φ of the counter 52 , and the same number of signals as the count value of the counter 52 are sent from the AND gate 48 to the shift register 42 . Two pulses will be provided.

The shift register 42 uses this AND gate 48
It is configured to shift the preset value by 1 bit in the lower direction every time a pulse from In the example embodiment, it is reduced by a factor of 4 by generating two pulses. This means that the output value of the shift register is 1/4 of the total sleep time, that is, the average sleep time per day.

The average sleep time of this shift register 42 and the actual sleep time counted by the counter 28 in the sleep time counter 26 are compared in a comparison circuit 54, and if the value of the counter 28 is smaller, the comparison circuit 54 detects Output a signal. This detection signal is input to a volume control circuit 58 connected between the alarm circuit 16 and the sound generation circuit 56. This circuit 5
Reference numeral 8 consists of a current limiting resistor 60 and a MOSTr 62 connected in parallel to the current limiting resistor 60. When a detection signal is supplied, the MOSTr 62 is turned on and the resistor 60 is bypassed.

As described above, according to this embodiment, the average value of sleep time for four days is stored in the shift register 42, and this average value is compared with the actual sleep time after this, and the actual sleep time is determined from the average value. If your sleep time is short, the alarm volume will be higher than usual.

Furthermore, in this embodiment, since it takes four days until the average sleep time is calculated for the first time, a specific sleep time is preset in the shift register 42 during this period. For this purpose, an initial clear circuit 64 that generates a pulse when the power is turned on;
An initial value setting circuit 66 is provided for presetting an initial value in the shift register 42 in response to this pulse. This circuit 66 includes an initial value memory 68 in which initial values are stored, and a quaternary counter 40 at a set input S.
FF70, to which the carry signal of FF is input, and the pulse of the initial clear circuit 64 is input to the reset input R;
and an AND gate 72 that controls supply of the initial value from the initial value memory 68 to the shift register 42 by the output of the AND gate 70 . Therefore, when the power is turned on, the output of the FF 70 becomes H level due to the pulse from the initial clear circuit 64, opening the AND gate 72, and supplying the initial value from the initial value memory 68 to the shift register 42. do. Since this pulse enables the shift register 42 to be preset at the same time, the shift register 42 is preset to an initial value. When the total sleep time counter 36 counts the sleep time for four days, a carry signal is output from the quaternary counter 40 and the output of the FF 70 is set to L level.
Instead, the count value of the total sleep time counter 36 is preset and divided by 1/4.

In this way, only for the first four days, the alarm volume is controlled depending on whether the sleep time is longer or shorter than a specific sleep time.

(Effects of the invention) As described above, according to the invention, since the user's average sleeping time is used as the standard for volume control, the alarm sound can be generated at the most suitable volume for the user. , the user can be woken up without waste and surely.

[Brief explanation of the drawing]

The drawing is a circuit diagram of an alarm clock according to an embodiment of the present invention. 16...Alarm circuit, 26...Sleep time counter, 36...Total sleep time counter, 40...
Operation count counter, 42...Shift register, 4
6...Shift pulse generation circuit, 54...Comparison circuit, 58...Volume control circuit.

Claims (1)

[Claims for Utility Model Registration] An oscillator circuit, a frequency divider circuit that divides the frequency of a signal from the oscillation circuit, a time display section that displays the time based on the frequency-divided output signal from the frequency divider circuit, and an alarm set. an alarm switch for setting non-setting;
An alarm circuit outputs an alarm notification signal when the time displayed on the time display reaches a preset time when the alarm switch is in the set state, and an alarm circuit outputs an alarm notification signal from the alarm circuit. and a sound generation circuit that generates a sound, the time from when the alarm switch is operated to a set state to when it is operated to a non-operated state is counted using a divided output signal from the frequency dividing circuit. A sleep time counter and the number of times the alarm switch is operated from a set state to a non-set state are counted ²ⁿ (n=
When the alarm switch is operated to the set state, the frequency division output signal from the frequency dividing circuit starts counting, and the carry signal of the operation frequency counter is generated. a shift register in which the count value of the total sleep time counter is preset in response to a carry signal of the operation number counter; and a carry signal of the operation number counter. a shift pulse generation circuit that outputs a pulse signal for shifting the count value to the lower n bits which is preset in the shift register in response to the occurrence of a shift pulse; an initial clear circuit that outputs a clear pulse signal when the power is turned on; and this initial clear circuit. an initial value setting circuit that presets a preset value in the shift register in response to a pulse signal from the sleep time counter, and compares whether the count value of the sleep time counter is smaller than the count value of the shift register, and if it is smaller, A timepiece with an alarm, comprising: a comparison circuit that outputs a detection signal; and a volume control circuit that increases the volume of the alarm generated from the sound generation circuit when the detection signal from the comparison circuit is generated.