JPH0443837Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a watch with a snooze function, and particularly to one in which the switch operation for temporarily stopping the alarm notification sound is changed for each snooze operation.

(b) Prior art As a conventional clock of this kind, the
There is one shown in Publication No. 24670.

In general watches having a snooze function, including this watch, if the snooze switch is operated during alarm notification, the notification sound will temporarily stop, and the notification sound will be emitted again after a certain period of time.

The watch repeats this operation until the ringing switch is turned off.

(c) Problems to be solved by the invention In the conventional example described above, the alarm notification sound can be temporarily stopped by simply operating the snooze switch.

As described above, in the past, the notification could be stopped with a very simple operation, which caused the problem that the user had difficulty getting up.

(d) Means for solving the problem The purpose of the present invention is to make it possible for the user to wake up earlier by making it impossible to temporarily stop the alarm sound without performing a more complicated switch operation. .

In order to solve the above problems and achieve the purpose, the present invention inputs operation signals from a plurality of correction switch groups, a notification signal from a snooze circuit, and a count output signal from a snooze counter, and A switch switching circuit that prevents the operation signal from being applied to the time display section only when the signal is generated, and selects and outputs one of the operation signals according to the count output signal, and from this switch switching circuit. The present invention is characterized in that a simultaneous operation detection circuit is provided, which applies a signal to the snooze circuit to stop the notification when it detects that the operation signal from the snooze switch and the operation signal from the snooze switch are generated simultaneously.

That is, the switch to be operated changes depending on the number of snooze operations, and the alarm notification sound cannot be temporarily stopped unless one of the plurality of correction switches and the snooze switch are operated at the same time.

(e) Examples Examples of the present invention will be described below based on the drawings. FIG. 1 is a diagram showing a circuit configuration of a watch with a snooze function according to an embodiment of the present invention.

2 is a reference signal generator that outputs a reference signal. 4 is a time display unit that inputs a reference signal and displays the time, and a frequency dividing circuit 6 that divides the frequency of the reference signal.
, a clock circuit 8 that counts the frequency-divided signal that it outputs, a decoder/driver 10 that changes the time signal that it outputs into a display drive signal, and a display section that inputs the display drive signal that it outputs and displays the time. It consists of 12.

Reference numeral 14 designates a reference circuit, which includes an alarm memory 16 that stores the set alarm time, and a matching circuit 18 that inputs and compares the stored contents and a signal indicating the count contents of the clock circuit 8, and outputs a detection signal A when they match. It is composed of.

20 is a snooze circuit, the detailed circuit configuration of which is shown in FIG.

This snooze circuit 20 consists of an AND gate 22 that inputs a detection signal A from a coincidence circuit 18 and an operation signal B from a ring stop switch 40, and a one-channel circuit that generates a pulse in an output signal C in response to the rising edge of the output signal. Yotsuto Multivibrator (hereinafter abbreviated as OSM) 24 and AND Gate 22
an inverter 28 that inverts the output signal of the inverter 28, an OR gate 30 that inputs the output signal thereof and a signal K from a snooze counter described later, and an OSM 26 that outputs a pulse to the output signal D in response to the rising edge of the output signal. A flip-flop which inputs a signal C and a signal J from a snooze counter (described later) to a set input S via an OR gate 34, and inputs a signal D and a signal I from a simultaneous operation detection circuit (described later) to a reset input R via an OR gate 36. (hereinafter abbreviated as FF) 32 and signals C and D are input to the set input S and reset input R, respectively.
It is composed of FF38.

42 is a sound generation circuit, which is in the snooze circuit 20.
When the notification signal E from the FF 32 is input, an alarm notification sound is generated based on the clock signal φ ₂ from an intermediate stage of the frequency dividing circuit 6.

44 is a snooze counter, which receives the clock signal _φ1 from the middle stage of the frequency dividing circuit 6 as the clock input φ.
A counter 48 inputs a signal H from the FF 38 in the snooze circuit 20 and a signal I from a simultaneous operation detection circuit (described later) to a reset input R via an OR gate 46, and outputs a signal J from an output C. It is.

50 is a snooze number counter, the signal F from the FF32 in the snooze circuit 20 is applied to its clock input φ, the signal H from the FF38 in the snooze circuit 20 is applied to the reset input R, and the output A signal K is output from C.

Reference numeral 52 indicates correction switches, including a second reset switch 54, a minute correction switch 56, and an hour correction switch 5.
It consists of 8.

60 is a snooze switch.

62 is a switch changeover circuit, the detailed circuit configuration of which is shown in FIG.

This switch switching circuit 62 inputs the inverted notification signal E from the snooze circuit 20 to each input terminal, and inputs the operations from the seconds reset switch 54, minute correction switch 56, and hour correction switch 58 to each other input terminal. AND gates 64, 66, and 68 input signals M ₁ , M ₂ , and M _{3 ,} respectively; signal E is input to each first input terminal; and signal Q from the snooze number counter 50 is input to each second input terminal; ₄ , Q ₃ and Q ₂ , respectively, and further input signals M _{1 and} Q 2 to each third input terminal.
AND gate 70 which inputs M ₂ and M ₃ respectively,
72, 74 and this AND gate 70, 72, 7
The OR gate 76 inputs the four output signals O ₁ , O ₂ , O ₃ and outputs the signal P.

AND gate 6 in this switch switching circuit 62
The signals N ₁ , N ₂ , N ₃ output by 4, 66, 68 are:
Reset input R of seconds counter 86 in timekeeping circuit 8 and minute counter 9 via OR gate 88, respectively.
0 is applied to hour counter 94 via OR gate 92.

78 is a simultaneous operation detection circuit, the detailed circuit configuration of which is shown in FIG.

This simultaneous operation detection circuit 78 includes an AND gate 80 which inputs the operation signal L from the snooze switch 60 and the signal _Q1 from the snooze counter 50 and outputs the signal _R2 , and the signal L and switch switching circuit 6.
It is comprised of an AND gate 82 which inputs the signal P from 2 and outputs the signal R ₁ , and an OR gate 84 which inputs the signals R ₁ and R ₂ and outputs the signal I.

Next, the operation of the snooze function watch of this embodiment having the above configuration will be explained based on the time charts shown in FIGS. 4 and 5.

At the now set alarm time, the matching circuit 18 detects that the count content of the timer circuit 8 and the stored content of the alarm memory 16 match, and sets its output signal A to H level.

If the ring stop switch 40 is on at this time, the AND gate 22 in the snooze circuit 20
The output signal of C becomes H level, and OSM 24 generates a pulse in the output signal C in response to the rising edge.

This pulse is input to each set input S of FF32 and FF38.
is applied to set these FFs 32 and 38.

When the FFs 32 and 38 are set, their output signals E and G go to the H level, and the output signals F and H go to the L level, so that the sound generation circuit 42 to which the signal E is input generates an alarm sound.

At this time, the snooze number counter 50 is reset.

At this time, the output signal _Q1 is at H level. In this way, when the output signal _Q1 of the snooze number counter 50 is at H level, the AND gate 8 in the simultaneous operation detection circuit 78 which inputs this signal _Q1
0 becomes open.

Therefore, when the snooze switch 60 is turned on and an operation pulse is generated in its output signal L,
This operation pulse is the output signal of the AND gate 80.
R ₂ and passes through OR gate 84 to signal I.

The pulse generated in this signal I is applied to the reset input R of the FF 32 in the snooze circuit 20,
Reset this.

Therefore, the output signals E and F of the FF 32 become L and H levels, respectively, and the sound generation circuit 42 to which the signal E is input stops generating the alarm notification sound.

The pulse generated in signal I also resets counter 48 in snooze counter 44, so that counter 48 begins counting in response to clock signal _φ1 .

Then, after counting for a certain period of time, the output C
A pulse is generated in the signal J from.

The pulse generated in this signal J is applied to the set input S of the FF 32 in the snooze circuit 20, and this FF 32 is set again to output its output signals E,
Switch F to H and L levels.

When this signal E becomes H level, the sound generation circuit 42 generates the alarm notification sound again.

On the other hand, when the signal F becomes H level, the snooze counter 50 is activated in synchronization with this rise.
has already advanced its count by 1, and the output signal
The output signal _Q2 is set to H level instead of _Q1 .

Here, in order to stop the alarm notification sound, it is necessary to operate the snooze switch 60 and the hour adjustment switch 58 at the same time.

That is, since the output signal E of the snooze circuit 20 and the output signal _Q2 of the snooze number counter 50 are at H level, the AND gate 74 in the switch switching circuit 62 is in an open state.

Therefore, when the hour correction switch 58 is turned on, the operation pulse generated in the output signal _M3 is
The output signal O ₃ of this AND gate 74 is generated.

The pulse generated in the signal O ₃ is generated in the signal P via the OR gate 76 and applied to the AND gate 82 in the simultaneous operation detection circuit 78 .

At this time, if the snooze switch 60 is not operated, the signal L from the snooze switch 60 is
The output signal R ₁ of the AND gate 82 inputting
When the time correction switch 58 and the snooze switch 60 are turned on at the same time, pulses are generated in the signals P and L at the same time, and a pulse is generated in the output signal _R1 of the AND gate 82.

The pulse generated in the signal _R1 is generated in the output signal I through the OR gate 84, and similarly to the operation described above, the FF 32 in the snooze circuit 20 is reset to stop the alarm notification sound. Moreover, as mentioned above, the snooze counter 44
When a pulse is generated in this signal I, counting is started.

Thereafter, a pulse is generated in the output signal J of the snooze counter 44, the FF 32 is set, and the alarm notification sound is generated again.

Further, when the signal F reaches the H level, the snooze number counter 50 has already set its output _Q3 to the H level in synchronization with the rising edge of the signal F.

Therefore, the AND gate 72 in the switch switching circuit 62 is now in an open state, and when the minute correction switch 56 is turned on, a pulse is generated in its output signal _O2 .

This pulse is generated in the signal P via the OR gate 76, and if the snooze switch 60 is turned on at the same time in the same manner as described above, a pulse is generated in the signal I via the AND gate 82 and the OR gate 84.

As a result, the alarm notification sound is stopped again.

Also, at this time, the count of the snooze number counter 50 is advanced in the same manner as the operation described above,
When the output signal _Q4 becomes H level and alarm notification starts, the switch switching circuit 6
When the second reset switch 54 is turned on and the second reset switch 54 is turned on, a pulse is generated in the output signal _O1 .

This pulse is also generated in the signal P via the OR gate 76, and at this time, if the snooze switch 60 is turned on, a pulse is generated in the signal I via the AND gate 82 and the OR gate 84, and the alarm notification sound is again generated. Stop.

In this embodiment, each time the snooze counter 50 counts the number of snooze operations, the AND gates 80, 74, 72 in the simultaneous operation detection circuit 78 and the switch switching circuit 62,
70 are sequentially opened, and the switches whose ON operation becomes effective are changed over.

Further, after the second snooze operation, unless one of the snooze switch 60 and the correction switch 52 is operated at the same time, no pulse is generated in the signal I, and the alarm notification sound cannot be stopped.

Furthermore, the AND gate 6 in the switch switching circuit 62
4, 66, and 68 are open when the notification signal E is at L level (not in the alarm notification state), and the second reset switch 54 and the minute correction switch 5
6. Operation signals M ₁ , M ₂ of the hour adjustment switch 58,
Each pulse generated in _M3 is its output signal
N ₁ , N ₂ , and N ₃ to reset the second counter 86 or to fast-forward the count values of the minute counter 90 and hour counter 94 to correct the time.

Also, when the ring stop switch 40 is turned off and its output signal B is set to L level, or when the snooze counter 50 counts a certain number and generates a pulse in its output signal K, the OR gate in the snooze circuit 20 30 becomes H level, and in response to this rise, a pulse is generated in the output signal D of OSM 26.

This pulse is applied to the reset input R of FFs 32 and 38 to reset them.

When the FFs 32 and 38 are reset, the alarm notification sound stops, the snooze counter 44 and the snooze counter 50 are maintained in a reset state, and the alarm notification is completely stopped.

(f) Effects of the invention According to the invention, the switch to be operated changes each time the snooze operation is performed, and it is necessary to operate the snooze switch and another switch at the same time, so it is difficult for the user to stop the notification. It's less difficult and you can wake up earlier.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a snooze function watch according to an embodiment of the present invention, FIG. 2 is a diagram showing the circuit configuration of the snooze circuit shown in FIG. 1, and FIG. 3 is the diagram shown in FIG. 1. Figures 4 and 5, which show the circuit configurations of the switch switching circuit and the simultaneous operation detection circuit, are time charts. 2...Reference signal generation circuit, 4...Time display section,
14...Reference circuit, 20...Snooze circuit, 42
... Sound generation circuit, 44 ... Snooze counter, 50
... Snooze number counter, 52 ... Correction switch, 60 ... Snooze switch, 62 ... Switch switching circuit, 78 ... Simultaneous operation detection circuit.

Claims (1)

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal, a time display section that displays the time using the reference signal from the reference signal generator, and a time display section that corrects the time displayed on the time display section. a plurality of correction switches for the time display, a reference circuit for detecting that the time displayed on the time display section has reached a preset time, a snooze switch, and a snooze switch responsive to generation of a detection signal from the reference circuit. a snooze counter that enables counting of the reference signal from the reference signal generator, clears the count value with an operation signal from the snooze switch, and outputs a carry signal when the count value reaches a constant value; , a snooze circuit that outputs a notification signal from the time when the detection signal from the reference circuit or the carry signal from the snooze counter is generated until the time when the snooze switch is operated; a snooze counter that outputs a notification stop signal that causes the snooze circuit to stop generating the notification signal when the value reaches a certain value; and a sound generator that generates a notification sound in response to the notification signal from the snooze circuit. A watch with a snooze function, which is connected between the plurality of correction switches and the time display section, and receives a notification signal from the snooze circuit and a count output signal from the snooze counter, When the notification signal is generated, the operation signals of the correction switch group are prevented from being supplied to the time display section, and the correction switch group is operated in accordance with the count output value of the snooze operation counter. a switch switching circuit for selectively outputting one of the signals; and supplying an output signal to the snooze circuit when it is detected that an operating signal from the switch switching circuit and an operating signal from the snooze switch are generated simultaneously. A timepiece with a snooze function, comprising: a simultaneous operation detection circuit; and an output signal from the simultaneous operation detection circuit is supplied to the snooze circuit instead of an operation signal from the snooze switch.