JPH0444006U

JPH0444006U -

Info

Publication number: JPH0444006U
Application number: JP8696290U
Authority: JP
Priority date: 1990-08-20
Filing date: 1990-08-20
Publication date: 1992-04-14

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の要部構成図、第２
図は第１図のコントローラが適用されたシステム
の構成図、第３図は第２図のシステムの具体的構
成図、第４図は第２図のシステムの動作説明図、
第５図は従来における電源投入シーケンスコント
ローラの構成例を示した図である。１……マスタシステム、２……スレーブシステ
ム、７……トリガ信号発生回路、８，８_１，８_２……コントロール信号発生回路、９_１，９_２……
電源。 Figure 1 is a configuration diagram of the main parts of an embodiment of the present invention, Figure 2
The figure is a configuration diagram of a system to which the controller of Figure 1 is applied, Figure 3 is a specific configuration diagram of the system of Figure 2, and Figure 4 is an explanatory diagram of the operation of the system of Figure 2.
FIG. 5 is a diagram showing an example of the configuration of a conventional power-on sequence controller. 1...Master system, 2...Slave system, 7...Trigger signal generation circuit, 8, 8 ₁ , 8 ₂ ... Control signal generation circuit, 9 ₁ , 9 ₂ ...
power supply.

Claims

[Claims for Utility Model Registration] In a power-on sequence controller for turning on power to a master bus system and a slave bus system, the controller is provided in each of the master bus system and slave bus system, and is turned on and off by a control signal. first and second power supplies that supply power to the bus system and the slave bus system; a trigger signal generation circuit that generates a trigger signal that triggers power on/off operations; a first control signal generation circuit that applies a control signal to the first power supply to drive the first power supply after a delay time has elapsed; A power-on sequence controller comprising: a second control signal generation circuit that is driven by being supplied with a power source and whose delay time is shorter than the delay time of the first control signal generation circuit.