JPH0444051U - - Google Patents
Info
- Publication number
- JPH0444051U JPH0444051U JP8695990U JP8695990U JPH0444051U JP H0444051 U JPH0444051 U JP H0444051U JP 8695990 U JP8695990 U JP 8695990U JP 8695990 U JP8695990 U JP 8695990U JP H0444051 U JPH0444051 U JP H0444051U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- processor
- main processor
- bus
- bits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Description
第１図は本考案を実施したデータ・アクセス制
御装置の全体構成図、第２図及び第３図は本考案
装置の動作を表わすタイムチヤート、第４図は本
考案回路における制御回路の構成を表わす回路図
、第５図は従来のデータ・アクセス制御回路の全
体構成図、第６図及び第７図は従来の回路の動作
を表わすタイムチヤートである。
１……メイン・プロセツサ、２……Ｉ／Ｏバス
、３……スレーブ・プロセツサ、４……８ビツト
・データ・バス、５……３２ビツト・カウンタ、
６……ＲＡＭ、７……バス・インターフエイス、
８……制御回路。
Figure 1 is an overall configuration diagram of a data access control device embodying the present invention, Figures 2 and 3 are time charts showing the operation of the device of the present invention, and Figure 4 shows the configuration of the control circuit in the circuit of the present invention. FIG. 5 is an overall configuration diagram of a conventional data access control circuit, and FIGS. 6 and 7 are time charts showing the operation of the conventional circuit. 1... Main processor, 2... I/O bus, 3... Slave processor, 4... 8-bit data bus, 5... 32-bit counter,
6...RAM, 7...Bus interface,
8...Control circuit.
Claims (1)
、このメイン・プロセツサが扱うビツト数より小
さいビツト数を扱うスレーブ・プロセツサとを有
し、前記スレーブ・プロセツサが扱うビツト数で
前記メイン・プロセツサから数回に亘つて前記ス
レーブ・プロセツサ側とデータ転送するデータ・
アクセス制御回路において、前記メイン・プロセ
ツサまたは前記スレーブ・プロセツサから前記Ｉ
／Ｏバス使用中信号を受け、アクセス中でない装
置から送出されたバス権要求信号を現在のアクセ
スが終了するまで受け付けないようにした制御回
路を設けたことを特徴とするデータ・アクセス制
御回路。 It has a main processor connected to an I/O bus, and a slave processor that handles a smaller number of bits than the main processor, and the slave processor handles a number of bits smaller than the number of bits handled by the main processor. The data to be transferred to and from the slave processor over multiple times.
In the access control circuit, from the main processor or the slave processor to the I
1. A data access control circuit comprising: a control circuit that receives a /O bus busy signal and does not accept a bus request signal sent from a device that is not accessing until the current access is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8695990U JPH0444051U (en) | 1990-08-20 | 1990-08-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8695990U JPH0444051U (en) | 1990-08-20 | 1990-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444051U true JPH0444051U (en) | 1992-04-14 |
Family
ID=31818920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8695990U Pending JPH0444051U (en) | 1990-08-20 | 1990-08-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444051U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01211161A (en) * | 1988-02-19 | 1989-08-24 | Nec Corp | Information processor |
-
1990
- 1990-08-20 JP JP8695990U patent/JPH0444051U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01211161A (en) * | 1988-02-19 | 1989-08-24 | Nec Corp | Information processor |
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