JPH0444738U

JPH0444738U -

Info

Publication number: JPH0444738U
Application number: JP8774090U
Authority: JP
Priority date: 1990-08-22
Filing date: 1990-08-22
Publication date: 1992-04-16

Description

[Brief explanation of the drawing]

第１図は、本考案の実施例における主要ブロツ
ク図。第２図は、本考案の実施例にでてくるＢＣ
Ｈ３１，２１符号３１ビツトと、前記ＢＣＨ３１
，２１符号に対するパリテイ・チエツク・ビツト
１ビツト、計３２ビツトから成る符号の従来の１
ビツト誤り検出訂正回路のブロツク図。第３図は
、本考案の実施例にでてくるＢＣＨ３１，２１符
号３１ビツトと、前記ＢＣＨ３１，２１符号に対
するパリテイ・チエツク・ビツト１ビツト、計３
２ビツトから成る符号の従来の２ビツト誤り検出
訂正回路のブロツク図。第４図は、第１図の本実
施例における主要ブロツク図を、本実施例の動作
を説明し易いように少し具体化したブロツク図。
第５図は、第４図における誤り検出回路１０８を
より具体化したブロツク図。第６図は、第４図に
おける誤り検出回路１０８における動作を説明す
るためのタイミング・チヤート図。 FIG. 1 is a main block diagram of an embodiment of the present invention. Figure 2 shows the BC that appears in the embodiment of this invention.
H31, 21 code 31 bits and the BCH31
, 1 parity check bit for 21 codes, a total of 32 bits.
A block diagram of a bit error detection and correction circuit. FIG. 3 shows 31 bits of the BCH31, 21 code appearing in the embodiment of the present invention and 1 parity check bit for the BCH31, 21 code, a total of 3 bits.
1 is a block diagram of a conventional 2-bit error detection and correction circuit for a code consisting of 2 bits; FIG. FIG. 4 is a block diagram in which the main block diagram of the present embodiment shown in FIG. 1 is slightly more specific in order to make it easier to explain the operation of the present embodiment.
FIG. 5 is a block diagram illustrating the error detection circuit 108 in FIG. 4 in more detail. FIG. 6 is a timing chart for explaining the operation of the error detection circuit 108 in FIG. 4.

Claims

[Scope of utility model registration request]

Of the code decoding circuits consisting of a BCH code and parity check bits for the BCH code, a first one calculates the syndrome of the BCH code.
an error magnitude calculation circuit that calculates error magnitude information using the first syndrome information as input; and an error position that calculates error location information for the BCH code using the first syndrome information as input. a calculation circuit; an error correction circuit that receives the error position information and calculates error correction information of the BCH code; a second syndrome calculation circuit that calculates a syndrome of data error-corrected by the error correction circuit; an error detection circuit that calculates the presence or absence of an error using second syndrome information as an input; and a parity check circuit that performs a parity check using the data error-corrected by the error correction circuit and the parity check bit as input. an error detection and correction circuit comprising: a selection means for selecting an error detection capability; the error magnitude information; the error presence/absence information;
and an error detection circuit that performs error detection by rearranging and using three pieces of information output from the parity check circuit according to the output of the error detection capability selection means. Detection correction circuit.