JPH0444906U

JPH0444906U -

Info

Publication number: JPH0444906U
Application number: JP8606590U
Authority: JP
Priority date: 1990-08-14
Filing date: 1990-08-14
Publication date: 1992-04-16
Anticipated expiration: 2005-08-14
Also published as: JP2530237Y2

Description

[Brief explanation of the drawing]

第１図は本考案の実施例１のブロツク図、第２
図は本考案の実施例２のブロツク図、第３図は実
施例２の実行手順の図、第４図は実施例２の他の
実行手順の図、第５図は実施例２の更に他の実行
手順の図、第６図は実施例２の更に他の実行手順
の図、第７図は本考案の実施例３のブロツク図、
第８図は実施例３の他の回路のブロツク図、第９
図は実施例３の更に他の回路のブロツク図、第１
０図は第９図の実施例の搬送波発振器の発振周波
数の変化を示す図である。１……エレメントアレイ、７，７′……光磁気
デイスク装置、８……ＲＦバイアス発振回路、９
，４１，４６，５６……加算器、１２……遅延加
算適応化部、２２……送波ビームフオーマ、２３
，４０，５５……受波ビームフオーマ、２４……
位相検波器群、２５，４５……ＰＡＣコントロー
ラ、２６……遅延修正用一時記憶装置、２７……
システムコントローラ、４２……ダイナミツクフ
イルタ、４３……位相検波器、５１……可変デイ
レーライン、５２……検波器、５７，５８……標
準化回路、５９……割算器。 Figure 1 is a block diagram of the first embodiment of the present invention, and Figure 2 is a block diagram of the first embodiment of the present invention.
The figure is a block diagram of the second embodiment of the present invention, FIG. 3 is a diagram of the execution procedure of the second embodiment, FIG. 4 is a diagram of another execution procedure of the second embodiment, and FIG. 5 is a diagram of another execution procedure of the second embodiment. FIG. 6 is a diagram of still another execution procedure of the second embodiment, FIG. 7 is a block diagram of the third embodiment of the present invention,
FIG. 8 is a block diagram of another circuit of the third embodiment, and FIG.
The figure is a block diagram of still another circuit of Embodiment 3.
FIG. 0 is a diagram showing changes in the oscillation frequency of the carrier wave oscillator of the embodiment of FIG. 9. 1... Element array, 7, 7'... Magneto-optical disk device, 8... RF bias oscillation circuit, 9
, 41, 46, 56... Adder, 12... Delay addition adaptation unit, 22... Transmission beam former, 23
, 40, 55... Reception beam former, 24...
Phase detector group, 25, 45... PAC controller, 26... Temporary storage device for delay correction, 27...
System controller, 42... Dynamic filter, 43... Phase detector, 51... Variable delay line, 52... Detector, 57, 58... Standardization circuit, 59... Divider.

Claims

[Claims for Utility Model Registration] (1) An element array 1 having a plurality of elements EL ₀ to EL ₆₃ , a recording device 7 for recording a received signal, and a delay with respect to a reproduced signal from the recording device 7. An ultrasonic imaging apparatus characterized by comprising a delay addition adaptation unit 12 that performs phase error correction after addition. (2) An element array 1 having a plurality of elements EL ₀ to EL ₆₃ , and a reception beamformer 23 equal to the number of elements for each element to perform phasing and addition of signals received by the element array 1; a phase detector group 24 that performs phase detection of the received signal, a PAC controller 25 that calculates the phase error of the signal of each element EL ₀ to EL ₆₃ from the output signal of the phase detector group 24, and a PAC controller 25 that temporarily stores the phase error data. A delay correction temporary storage device 26 that stores data and outputs it as data for changing the delay amount of the receiving beamformer 23 in order to correct the phase error of the received signal that is input afterwards; and a data collection and image for phase error correction. An ultrasonic imaging apparatus characterized by comprising a system controller 27 that controls the timing of data acquisition and enables image display using phase error corrected data in real time. (3) Element array 1 having a plurality of elements EL ₀ to EL ₆₃ , and each element EL ₀ to _{EL 63} having one element each.
receiving beamformer ₄₀₀ to 40 connected to
₆₃ , and an adder 41 that adds the outputs of each receiving beamformer ₄₀₀ to ₄₀₆₃ and outputs phasing addition data.
And, the output of each of the elements EL ₀ to EL ₆₃ is 1
a phase detector 43 which performs phase detection by inputting the received signal to be corrected of one channel sequentially input channel by channel and the adjacent channel or the output of the adder 41 as a reference signal; A dynamic filter 42 is inserted into the signal line and shifts the center of the passband according to the passage of time after transmission, that is, the depth of the reflector, to achieve optimal reception; PAC controller 4 that calculates and stores the amount of error
5, and add and input the phase error amount and beam steering control signal to each receiving beamformer ₄₀₀ to ₄₀₆₃ ,
An ultrasonic imaging apparatus characterized by comprising an adder 46 that adjusts a delay amount from _{0 0} to 40 ₆₃ to perform phase error correction. (4) An element array 1 having a plurality of elements EL ₀ to EL ₆₃ , a variable delay line 51 that delays the received signal from each element EL ₀ to EL ₆₃ , and a variable delay line 51 that delays the received signal from each element EL 0 to EL 63, and a carrier wave oscillator 53 that outputs two signals with a 90° phase difference and whose oscillation frequency changes correspondingly; and a detector that receives the received signal and the output signal of the carrier wave oscillator 53 and outputs two detected signals i and q. 52, a standardization circuit 57 that converts the input output signal of the detector 52 into data of a constant vector value, and performs phasing and addition of i and q detection outputs of all received signals from all elements EL ₀ to EL ₆₃ . a standardization circuit 58 that converts the input output signal of the adder 56 into constant vector value data; an ultrasonic imaging apparatus, comprising a divider 59 which receives an output and divides the two to obtain a phase difference therebetween and changes the amount of delay of the variable delay line 51.