JPH0445030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal readout method for a solid-state imaging device. This is a readout method that uses the capacitor of the signal readout line in the address method, and all of the main electrodes of the SIT are used as address lines or signal readout lines, and the pixel separation characteristics are good and images can be detected stably, uniformly, and with high sensitivity. The present invention provides a signal readout method for a solid-state imaging device with low power consumption, high speed, and large capacity.

The present invention can be applied to television cameras for broadcast stations, video cameras for home use, electronic still cameras, etc., as well as astronomical observation instruments that utilize high sensitivity and precision measuring instruments for physics and chemistry that utilize high speed.

[Conventional technology]

Conventional static induction phototransistor (Static
In a two-dimensional solid-state imaging device using a gate accumulation method using an induction phototransistor (hereinafter abbreviated as SIPT), the source and drain of the SIPT serve as signal readout lines or address lines, respectively, and the structure and signal readout method of the two-dimensional solid-state imaging device This is disclosed in Japanese Unexamined Patent Publication No. 199277/1988 entitled "Two-dimensional solid-state imaging device."

The disclosed signal readout method will first be described as an example of a conventional technique.

FIG. 4a shows an example of the configuration method of this example, and FIG. 4b shows an example of the read pulse. C _ij is one pixel of this two-dimensional solid-state imaging device, and consists of one SIPT and a capacitor. The drain of SIPT of pixel C _ij is connected to the signal readout line SL _i , and the source is connected to the buried line
At BL _j , the gate is connected to the vertical address line through a capacitor to GL _j . A precharge transistor Q _P is connected to the signal readout line SL _i , and is connected to a precharge power supply V _P through this Q _P. This Q _P has a common gate, and a precharge pulse φ _P is applied. Furthermore, SL _i is connected to a switch transistor Q _S through a transfer transistor Q _T . Q _T
The gates are shared, and a transfer pulse φ _T is applied. The gate of Q _S is led to a horizontal shift register 42 . Q _S is connected to the video supply Vv through a resistor R _L , and the output connects a transfer capacitor C _T commonly connected to Q _T and Q _S.
Obtained from the V _put terminal by the voltage drop across R _L due to making Q _S conductive and charging it with Vv.
Further, the buried line BL _j is grounded through the buried line selection transistor Q _B , the gate of Q _B connected to BL _j is connected to GL _j , and GL _j is led to the vertical shift register 41 .

The reading method will be explained with reference to FIG. 4b. First, when the transfer transistor Q _T is in a conductive state due to the transfer pulse φ _T ,
The signal readout line SL _i is passed through the precharge transistor Q _P by the precharge pulse Q _P.
and transfer capacitor C _T is charged by V _P . Next, pixel C _1j connected to vertical address line GL _j by vertical address pulse φ _Gj
~C _oj Each SIPT discharges according to the amount of incident light.
By cutting off φ _Gj and φ _T at the same time, pixel C _1j ~
The optical information of C _oj is stored as the discharge amount of the transfer capacitor _CT . horizontal shift register 42
Outputs are sequentially obtained from the V _put terminal by read pulses φ _S1 to φ _So from the V put terminal.

[Problem that the invention seeks to solve]

The two-dimensional solid-state imaging device using the above-mentioned SIPT is
This makes it possible to take advantage of the high photosensitivity inherent in SIPT.
In other words, pixels C _1j to C _oj on the vertical address line GL _j
The source of each SIT constituting the SIT is connected to a common buried line BL _j , and a buried line selection transistor Q _B is connected between BL _j and ground, and the gate of Q _B is connected to the vertical address line GL _j By connecting to the vertical address line GL _j , only BL _j becomes the ground plane potential at the same time as the vertical address line GL j is selected, suppressing crosstalk between pixels on the same signal readout line.

However, since SIPTs with higher photosensitivity have characteristics close to normally-on, SIPTs constituting pixels on which light with a light intensity close to the saturation light level is incident will be used as the source even when not selected. The leakage current flowing between the drains at zero gate bias is large. Such highly sensitive SIPT
Configuring a two-dimensional solid-state imaging device using the above method prevents leakage due to unselected pixels after the signal readout line (surface line SL) is charged by the precharge pulse φ _P. The voltage fluctuation of the signal readout line due to the influence of
It was necessary to provide characteristics close to off-state. Therefore, it was necessary to design the SIPT, which is inherently highly sensitive, with a slightly lower sensitivity by making it normally off.

In the two-dimensional solid-state imaging device described above, the SIPT sources of unselected pixels are separated from the ground potential by transistors, but the buried line to which the SIPT sources are connected has a certain capacitance with respect to ground. have. Even if this capacitance is small, the sum of all buried lines cannot be ignored. Therefore, until this capacitance is charged to some extent, the potential of the signal readout line fluctuates due to the leakage current of the SIPT of the non-selected pixel. In particular, the leakage current of SIPT increases when there is strong incident light.

Therefore, in the above-mentioned two-dimensional solid-state imaging device, in order to minimize the voltage fluctuation of the signal readout line due to unselected pixels, the capacitance of the buried line to the ground is kept low, and precharge (charging by the precharge power supply V _P of the signal readout line) is performed. In addition to optimizing the timing of the later vertical address pulse and transfer pulse, there are also limitations in the design conditions of SIPT, and the problems described above arise when applying SIPT under conditions of extremely high sensitivity. Ta.

[Means for solving problems]

In the aforementioned two-dimensional solid-state imaging device, each pixel
Since a bias voltage is applied to the SIPT via a signal readout line, this bias voltage fluctuates due to leakage caused by pixels connected to the same signal readout line. Therefore, in the readout method for a solid-state imaging device of the present invention, a bias voltage is applied to the SIPT of each pixel using an embedded line. The operating principle of the reading method according to the present invention will be explained using FIG.

FIG. 2a shows a readout circuit for one pixel. pixel
C _ij consists of a SIPT 20 and a gate capacitor 24, the source 21 of SIPT 20 is connected to the signal readout line SL _i 25, and the drain 22 is connected to the buried line
At BL _j , gate 23 is connected to vertical address line GL _j through a gate capacitor C _G 24 . SL _i 25 is grounded through a reset transistor Q _R , and a reset pulse φ _R is applied to the gate of Q _R. Further, SL _i is connected to a switch transistor Q _S through a transfer transistor Q _T , Q _S is grounded by a load resistor R _L , and the point of this R _L connected to Q _S is the output terminal 25 (V _put ). Become. A transfer pulse φ _T is applied to the gate of Q _T.
However, a read pulse φ _Si is applied to each gate of Q _S. BL _j is connected to the power supply voltage V _DD through a buried line selection transistor Q _B . GL _j is connected to the gate of Q _B , and a vertical address pulse φ _Gj is applied. C _SL is the capacitance that signal readout line SL _j has to ground, C _T is the capacitance that transfer line TL _i has to ground, and C _B
respectively represent the capacitance that BL _j has with respect to ground.

Figure 2b shows the timing chart of the readout pulse and the potential change of the transfer line TL _i .
The potential change between V _TLi and the output terminal 25 is shown.

At time _t1 , first, the transfer transistor _QT is turned on by the transfer pulse _φT , and the transfer line is coupled to the signal readout line _SLI . Next, at time _t2 , the reset transistor _QR is reset by the reset pulse _φR.
becomes conductive, and V _TLi becomes ground potential. time
After Q _R enters the cut-off state at t ₃ , a vertical address pulse φ _Gj is applied at time t ₄ . At this time, the buried line selection transistor Q _B becomes conductive, and
SIPT 20 is biased by the power supply voltage _VDD . At the same time, SIPT20 is the gate capacitor C _G 24
A pulse φ _Gj is applied through the SIPT 20, and a discharge current flows through the SIPT 20 in accordance with the amount of light incident on the SIPT 20 within a certain period. In Figure 2b, the changes in V _TLi are as follows: dotted line a is in the dark state, that is, when there is no incident light, dashed line b is in the normal light irradiation state, that is, when the amount of incident light is less than the saturated light amount, and solid line c is in the saturated light amount. This corresponds to the case where the incident occurs. When φ _T and φ _Gj are cut off at time t ₅ and Q _T enters the cut-off state, the optical information of the pixel C _ij obtained from the SIPT 20 is stored in C _T . Then time t ₆
The switch transistor Q S becomes conductive due to the read pulse φ _Si , and the switch transistor Q _S becomes conductive through the load resistance R _L.
CT is discharged and output is obtained. The change in V _put at this time depends on the value of V _TLi . When the incident light to the pixel C _ij is in a dark state, the dotted line a, when normal light irradiation, the dotted line a,
When the amount of light is saturated, it becomes like the solid line c.

[Effect]

In the readout method of the solid-state imaging device of the present invention, bias is applied to the SIPT constituting each pixel using an embedded line rather than a signal readout line, thereby applying a bias to the SIPT of the addressed pixel.
A constant bias voltage can be applied only and always. Therefore, a large-capacity two-dimensional solid-state imaging device can be read out stably and uniformly.

From time t ₄ to t ₅ in Fig. 2b, the SIPTs forming the pixels on the same signal readout line are biased to the opposite operation, and the SIPTs forming the non-selected pixels
It is possible that leakage current between the source and drain of SIPT may affect the signal readout line. However, SIPT in inverted operation has a smaller current amplification factor than SIPT in upright operation, and can be said to be a sufficient improvement over the conventional readout method described above.

〔Example〕

An embodiment of the readout method for a solid-state imaging device of the present invention is shown in FIG. 1, and an example of a device structure for one pixel is shown in FIG.

First, the configuration of a two-dimensional solid-state imaging device will be described using FIG. 1a.

One of the n×m pixels arranged in a two-dimensional matrix, C _ij , consists of one SIPT and a gate capacitor. The source of SIPT of this pixel C _ij is connected to the signal readout line SL _i , and the drain is connected to the buried line
At BL _j , the gate is connected to the vertical address line GL _j through a gate capacitor. BL _j and GL _j
are parallel and perpendicular to SL _i . The signal readout line SL _i is grounded through a reset transistor Q _Ri , and the gates of Q _R are all connected in common and a reset pulse φ _R is applied. Further, SL _i is connected to a switch transistor Q _Si through a transfer transistor Q _Ti . All gates of Q _T are made common, and transfer pulse φ _T is applied. Connect a suitable capacitor C _Ti to the connection between Q _Ti and Q _Si .
is provided, and Q _Si is further grounded by a suitable load resistor R _L common to all Q _S , and the point where this load resistor is connected to all Q _S is the output terminal V _put
It becomes 17. A read pulse φ _Si is applied to the gate of the switch transistor Q _Si through the horizontal shift register 12 . The buried line BL _j is connected to the power supply V _DD through the buried line selection transistor Q _Bj . The gate _of Q _Bj is connected to a vertical address line GL _j , which is guided to a vertical shift register 1, to which a vertical address pulse φ _Gj is applied.

FIG. 1b shows a timing chart of read pulses. The vertical shift register sequentially outputs vertical address pulses φ _G1 , ..., φ _Gn , but as shown in Fig. 2b
Now, it shows φ _Gj and the following φ _Gj+1 .

At time t ₁ , transfer pulse φ _T enters and transfer transistor Q _T becomes conductive. At time t ₂ , reset pulse φ _R causes the signal readout line to be grounded together with C _T through reset transistor Q _R. becomes electric potential. At time _t3 , vertical address pulse φ _Gj enters, and vertical address line GL _j
Each pixel C _1j , ..., C _oj on the top corresponds to the amount of incident light.
Charge C _T1 , ..., C _Ti . At time _t4 , φ _Gj is cut off at the same time as φ _T , and the optical information of C _1j , ..., C _oj is stored in the corresponding C _T1 , ..., C _Ti . After φ _T expires, the horizontal shift register receives the read pulse φ _S1 ,
..., φ _So is generated and the switch transistor
Q _S1 , . . . , Q _So are made conductive in sequence to discharge the charge stored in C _T through R _L , and the outputs of C _1j , . . . , C _oj are sequentially output as potential changes of V _put . In this way, when the optical information of C ₁ j, ..., C _oj in one horizontal row has been output by time t ₈ , next C _{1 j+1} , ..., C _oj+1
The same procedure is repeated to read out the optical information of .

In Figure 1a, Q _R , Q _T , Q _B , and Q _S are all shown as MOS transistors, but
All of these do not need to be MOS transistors; SIT, bipolar transistors,
It may be a JFET or the like.

An example of a device structure for one pixel will be explained using FIG.

FIG. 3a schematically shows the surface structure, and FIG. 3b schematically shows the cross-sectional structure taken along the line A-A'. In the example of the device structure shown here, the p-type Si substrate 3
The n-channel SIPT formed on 18, the conductive transparent electrode 311 made of polysilicon, etc., and the transparent insulating film 312 made of SiO ₂ form the p ⁺ gate 316 of the SIPT.
One pixel is constituted by a MOS capacitor constituted by .

In FIG. 3b, an n ⁺ region 314 is a source region of the SIPT, an n ⁺ region 315 is a drain region of the SIPT, an n ⁻ region 317 is a channel region of the SIPT, and a region 313 is an isolation region that separates each pixel. Although not shown in the figure, vertically adjacent pixels in FIG. 3a are similarly separated. source area 3
14 is a conductive transparent electrode 319 made of polysilicon or the like.
The electrodes are taken by. The electrode 34 is removed from the surface of the buried drain region 315. This is because the buried drain region 315 is continuous in the direction perpendicular to the plane of the paper in the figure, but from the surface
This is because an attempt is made to reduce the resistance by attaching a highly conductive electrode such as Al-Si.
The electrodes 311 of the gate capacitors are connected to vertical address lines 35 made of the same material, with a highly conductive material 36, such as Al--Si, placed over the lines 35 to reduce the resistance.

FIG. 3a shows a portion corresponding to the pixel C _ij . This is the part surrounded by the dashed line in the figure.
35 is a vertical address line GL _j , 34 is a buried line BL _j , and 39 is a signal read line S _i . BL _j 3
4 and GL _j 35 are parallel and perpendicular to 3Li39. The intersection is insulated by an insulating material such as SiO ₂ or PSG. Furthermore, in the figure, the signal readout line SL _i-1 31 and the embedded line BL _j-1 3
3. Vertical address line GL _j+1 37 is shown.
32, 38, and 310 are the same materials as 36, and are provided to reduce the resistance of SL _i-1 31, GL _j+1 37, and SL _i 39, respectively.

As explained above in the pixel configuration, all the wiring is on the surface, so the precharge transistor, transfer transistor, buried line selection transistor, and switch transistor for readout are fabricated on the same chip. That's easy. The transfer capacitor may use the stray capacitance of the wiring, or may be manufactured in the same way as the MOS capacitor on the gate of SIPT.

〔Effect of the invention〕

The signal readout method of the solid-state imaging device of the present invention is as follows:
of the pixel selected by the vertical address pulse.
Only the SIPT is biased, its bias voltage is always a constant value, and the SIPT of the selected pixel is upright operation, while the SIPT of unselected pixels on the same signal readout line is inverted. This is a method for stably and uniformly reading out a large-capacity solid-state imaging device, which has excellent weak light detection sensitivity because it is biased only when operating.

This is because the photocurrent amplification factor is larger in the upright operation of the SIPT than in the inverted operation, and the photocurrent amplification factor increases with the drain bias voltage. This is because, although the leakage current was large, crosstalk between pixels on the same signal readout line could be sufficiently suppressed.

FIG. 5 shows an example of the photoelectric conversion characteristics of one pixel when the pixel having the structure shown in FIG. 3 is read out by the method shown in FIG. The size of one pixel is 85μ×
It is 65μ. Power supply voltage is V _DD = 2V, load resistance R _L =
Light with a wavelength of 655 nm (red) is irradiated at 1 kΩ, optical integration time (period from one address to the next address) T _LI = 10 ms, and the horizontal axis is the amount of incident light (μW/cm ² ),
The vertical axis is the difference in output voltage V _put from the dark state ΔV _put (mV)
It shows. It can be seen that it has a wide dynamic range of 80 dB from a weak incident light amount of 10 ^-4 μW/cm ² to 1 μW/cm ² , and that the weaker the light, the more sensitive the signal readout can be.

In this way, the present invention can make full use of the high photosensitivity characteristics of SIPT, and can be used with a light integration time of 10ms.
It can detect light with an intensity of 10 ^-4 μW/cm ² .

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, where a shows the configuration, b shows the readout operation waveform, and FIG. 2 is a diagram for explaining the operation of the present invention, showing the operation of one pixel.
A shows the configuration, b shows the read operation waveform,
Fig. 3 shows an example of the configuration of one pixel, where a shows the surface structure and b shows the cross-sectional structure. Fig. 4 is a diagram for explaining the conventional technology, where a shows the structure and b shows the readout operation waveform. The figure shown in FIG. 5 is a diagram for showing the effect of the present invention, and is a diagram of photoelectric conversion confirmed by trial production and experiment. 14... Electrostatic induction phototransistor, 1... Source of electrostatic induction phototransistor, 2... Drain of electrostatic induction phototransistor, 3... Gate of electrostatic induction phototransistor, 13... Gate capacitor, 16... Power supply voltage, 15...Load resistance,
17...Output terminal ( _Vput ).

Claims (1)

[Claims] 1 Pixels C _ij composed of electrostatic induction phototransistors and gate capacitors are arranged in an n×m matrix, and vertical address lines GL _j (j=1 to m) are arranged.
is commonly connected to the gate of the electrostatic induction phototransistor constituting the pixel C _ij (i=1 to n) via the gate capacitor, and the signal readout line SL _i (i=1 to n) is connected to the gate of the electrostatic induction phototransistor constituting the pixel C ij (i=1 to n). _ij (j=1~
A buried line BL _j commonly connected to the sources of the electrostatic induction phototransistors constituting m)
(j=1 to m) are commonly connected to the drains of the electrostatic induction phototransistors constituting the pixels C _ij (i=1 to n), and the embedded lines BL _j (j
= 1 to m) is connected to a switch transistor Q _Bj , the gate of the switch transistor Q _Bj is connected to the vertical address line GL _j , and the signal readout line SL _i (i = 1 to n) is connected to two serial A predetermined capacitor is connected to the load resistor through the switch transistor Q _Ti and the switch transistor Q _Si connected to the switch transistor Q _Ti and the switch transistor Q _Si , and
In a two-dimensional solid-state imaging device having an output voltage C _Ti and a connection point between the load resistor and the switch transistor Q _S as an output terminal, all the electrostatic induction phototransistors operate in an erect state, and the drain bias voltage is Switch transistor Q _Bj (j=1~
m) through the signal readout line
SL _i (i=1 to n) is provided with a switch transistor Q _Ri for setting the signal readout line SL _i to ground potential before signal detection, and the switch transistor Q _Ti (i=1 to n) is conductive. When the switch transistor Q _Ri sets the signal readout line SL _i and the capacitor C _Ti to ground potential, one of the vertical address lines GL _j
(j=1 to m) inputs a vertical address pulse to select the pixel C _ij (i=1 to n), and according to the optical information of the pixel C _ij , the signal readout line SL _i and the capacitor C _Ti After charging the switch transistor Q Ti and turning off the switch transistor Q _Ti , the capacitor C _Ti is sequentially discharged through the switch transistor Q _Si (i=1 to n), thereby forming one column of the pixels C _ij (i=1 to n). A signal readout method for a solid-state imaging device, characterized in that the optical information of n) is read out.