JPH0445911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data demodulation method for demodulating data recorded on a magnetic recording medium such as a magnetic passbook.

Data recorded on a magnetic recording medium such as a magnetic passbook by the F2F method includes a preamble signal before the actual data, and this signal has a plurality of consecutive bits with the same code. Here is the F2F method
It is one of the FM (frequency modulation) methods, and the data on the magnetic recording medium is "1" if there is magnetic reversal between bit intervals, and "0" if there is no magnetic reversal.
It is. Data on this magnetic recording medium is read by a magnetic head and demodulated by a demodulator, but the data may jump when the magnetic head first contacts the magnetic recording medium, or when the data begins to be written to the magnetic recording medium. The first part of the data may be unstable and not guaranteed because the position of the data is not constant. Therefore, a method is used in which the first part of the data is omitted. However, with this method, the length of the unstable part of the data is not determined, so it is not possible to set the number of data omits, and depending on the data format, the preamble signal may be smaller than the number of ommits, making it difficult to actually It may be necessary to withhold data. Furthermore, since the preamble signal is reduced in quantity, it is disadvantageous when demodulating data including the preamble signal. That is, the preamble signal may also be regarded as valid data, and in this case it is not desirable to omit the first part of the data, and as a result, it is not possible to easily accommodate various data formats.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data demodulation method that can improve the above-mentioned drawbacks and can correctly demodulate data even if the front part of the data is unstable.

The present invention will be described below by way of examples with reference to the drawings.

FIG. 1 shows an apparatus used in an embodiment of the present invention, and FIG. 2 is a timing chart thereof.

When reading data, the magnetic head 11 comes into contact with a magnetic recording medium such as a magnetic passbook and moves relatively.
This magnetic recording medium, which reads data from the magnetic recording medium and inputs it to the demodulator 12, has data recorded using, for example, the F2F method, and this data has a preamble signal before the actual data (synchronization occurs before the start mark). ). This preamble signal has multiple bits of “0” at the front.
This "0" varies depending on the standard, but is, for example, 10 to 30 bits.

The demodulator 12 generates clock and data discrimination pulses from the input signal from the magnetic head 11, and uses these data discrimination pulses to discriminate whether the input signal is "1" or "0". The relative speed (data read speed) between the magnetic head 11 and the magnetic recording medium is detected by the clock, and the time width of the data discrimination pulse is varied according to this speed. That is, the demodulator 12 measures the interval of the previous bit, varies the time width of the data discrimination pulse, and masks the next data with this data discrimination pulse to discriminate whether it is "1" or "0". It uses a well-known variable mask method. This variable mask method operates correctly even when the data read speed changes, and is particularly effective in manual methods (methods in which the magnetic head and magnetic recording medium are manually moved relative to each other) where the data read speed is not constant. be.

The demodulator 12 outputs read data RDD and clock RCP via inverters I ₁ and I ₂ .
The read data from the inverter _I1 becomes high level when it is "0" and becomes low level when it is "1". According to the standard, the data recorded by F2F is set so that first a plurality of "0" bits follow, then a plurality of "1" bits follow, and then the actual data comes.

When data demodulation is started and the first clock is output from the demodulator 12, this clock is counted by the counter CNT and becomes "1".
The output terminal becomes high level. At this time, the counter
The "2" and "4" output terminals of the CNT remain at low level. Therefore, diode _D1 is off, diodes _D2 and _D3 are on, and the output of inverter _I3 becomes high level. On the other hand, the read data RDD of the demodulator 12 is at a low level, and the output of the NAND circuit _N1 is at a high level. Here, since the demodulation start signal is at a high level, the output of the NAND circuit _N2 becomes a low level, and the counter CNT is not reset.At the same time, the output of the inverter _I4 becomes a high level, and the demodulator 12 is also not reset.

Counter CNT is clocked from demodulator 12.
As the RCP is counted, the "1", "2", and "4" output terminals become high level in binary format. Therefore, the count number of counter CNT is 6.
Until then, one or two of the "1", "2", and "4" output terminals are at a low level, and the output of the inverter _I3 remains at a high level. At this time, if the read data RDD of the demodulator 12 remains at a low level, the state will not change. The count number of counter CNT is 7
When the output terminals ``1'', ``2'', and ``4'' all become high level, the diodes D ₁ , D ₂ , and D ₃ are all turned off, and the power supply voltage flows through the resistor R ₁ to the inverter I _{3 .}
given to. Therefore, the output of the inverter _I3 becomes low level, and the counter CNT becomes the enable terminal E.
When the signal becomes low level, it stops counting and the demodulator 12 is also not reset.

If the demodulator 12 erroneously reads "1" and the read data RDD becomes high level before the count number of the counter CNT reaches 7, the output of the NAND circuit N ₁ becomes low level and the NAND circuit N ₂ The output of CNT goes high, and the counter CNT and demodulator 12 are reset. Therefore, when the demodulator 12 is reset, the data discrimination pulse disappears, the read data RDD becomes low level, and data demodulation continues again. The counter CNT also counts the clock RCP from the demodulator 12 again. Thereafter, when the count number of the counter CNT reaches 7, the counter CNT stops counting as described above, and the demodulator 12 is no longer reset.

In this embodiment, the demodulator 12 is reset if the first 6 bits of data are checked and become "1" by mistake, but the number of bits to be checked can be set arbitrarily with reference to the data format. I can do it.

As described above, according to the present invention, before the demodulator demodulates a bit signal of the same code by a specified number of bits, it is detected that a bit signal of a different code has been demodulated and the demodulator is reset. Even if the data is unstable, it can be demodulated correctly, and when it is normal, it can be demodulated without cutting off the front part of the data, making it possible to support various data formats. Further, the above detection can be performed digitally and reliably.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an apparatus used in an embodiment of the present invention, and FIG. 2 is a timing chart of the same embodiment. 12...Demodulator, CNT...Counter, _I1 to _I4 ...
…Inverter, N ₁ , N ₂ … NAND circuit, D ₁ to _{D 3}
...Diode, R ₁ ...Resistor.

Claims (1)

[Claims] 1. In a data demodulation method in which a multi-bit signal of the same code at the front of data recorded on a magnetic recording medium is demodulated by measuring the interval of the previous bit with a demodulator, the demodulator demodulates the multi-bit signal of the same code. 1. A data demodulation method characterized in that the demodulator is reset by detecting that bits of another code have been demodulated before demodulating a bit signal by a predetermined number of bits.