JPH0446572U

JPH0446572U -

Info

Publication number: JPH0446572U
Application number: JP8741290U
Authority: JP
Priority date: 1990-08-23
Filing date: 1990-08-23
Publication date: 1992-04-21

Description

[Brief explanation of the drawing]

第１図は一実施例のプリント板上のパツド列の
配設説明図、第２図は一実施例のプリント板に実
装するメモリＩＣの構成図、第３図は第１図の構
成のパツド列，にメモリＩＣを実装した図、
第４図は第３図のＡ−Ａ断面図、第５図は第１図
の構成のパツド列，にメモリＩＣを実装した
図、第６図は第５図のＢ−Ｂ断面図、第７図は３
種類の大きさの異なる集積回路素子を実装できる
プリント板上のパツド列を説明する図である。１……プリント板、２ａ，２ｂ，……，３ａ，
３ｂ，……，３ａ′，３ｂ′，……パツド、４，
５……メモリＩＣ、６ａ，６ｂ，……，７ａ，７
ｂ，……，１０ａ，１０ｂ，……，１１ａ，１１
ｂ，……端子、８，８′……ハンダ、９……レジ
スト、〜……パツド列。 FIG. 1 is an explanatory diagram of the arrangement of pad rows on a printed board in one embodiment, FIG. 2 is a configuration diagram of a memory IC mounted on a printed board in one embodiment, and FIG. 3 is a diagram showing the arrangement of pad rows on a printed board in one embodiment. A diagram with memory ICs mounted in the column,
4 is a sectional view taken along line A-A in FIG. 3, FIG. 5 is a view showing a memory IC mounted on the pad row of the configuration shown in FIG. 1, and FIG. 6 is a sectional view taken along line B-B in FIG. Figure 7 is 3
FIG. 2 is a diagram illustrating pad rows on a printed board on which integrated circuit elements of different sizes can be mounted. 1...Printed board, 2a, 2b,..., 3a,
3b, ..., 3a', 3b', ...pad, 4,
5...Memory IC, 6a, 6b,..., 7a, 7
b, ..., 10a, 10b, ..., 11a, 11
b,...terminal, 8,8'...solder, 9...resist, ~...pad row.

Claims

[Claims for Utility Model Registration] (1) In a printed board on which an integrated circuit element is mounted having a pair of terminal rows arranged in a row at a predetermined terminal pitch, 1. A printed board comprising a pair of pad rows arranged in a row, each pad constituting the pad row extending in a direction perpendicular to the arrangement direction of the pad row. (2) In a printed board on which an integrated circuit element is mounted, which has a pair of terminal rows arranged in a row at a predetermined terminal pitch, the pads are arranged in a row at the same pitch as the terminal pitch of the integrated circuit element. a non-reference pad row provided in parallel with the reference pad row, each pad having the same pitch as the terminal pitch, and extending in a direction perpendicular to the arrangement direction of the reference pad row; A printed board characterized by having. (3) The printed board according to claim 2, wherein the non-reference pad row is covered with a resist material that divides each pad constituting the non-reference pad row in a direction perpendicular to its extending direction.