JPH0446785U

JPH0446785U -

Info

Publication number: JPH0446785U
Application number: JP8883390U
Authority: JP
Priority date: 1990-08-24
Filing date: 1990-08-24
Publication date: 1992-04-21

Description

[Brief explanation of the drawing]

第１図は本考案のコンバーゼンス調整信号発生
回路のブロツク図、第２図は本考案の格子パター
ン表示例の正面図、第３図は従来例の正面図であ
る。図中、１０はクロツク発生器、１０ａはクロツ
ク信号、１１はドツトカウンタ、１１ａ，１２ａ
および１３ａはアドレス信号、１２はラインカウ
ンタ、１３は加算器、１４は第２のメモリ、１４
ａは同メモリの出力データ、１５は第１のメモリ
、１５はシフトレジスタ、１７〜１９は増幅器、
２０〜２２は出力端子、２３はテレビ受像機、２
４は同テレビ受像機の表示画面、２５ａは同表示
画面の中心部調整点、２５ｂ〜２５ｆは周辺部調
整点である。 FIG. 1 is a block diagram of a convergence adjustment signal generating circuit according to the present invention, FIG. 2 is a front view of an example of a grid pattern display according to the present invention, and FIG. 3 is a front view of a conventional example. In the figure, 10 is a clock generator, 10a is a clock signal, 11 is a dot counter, 11a, 12a
and 13a is an address signal, 12 is a line counter, 13 is an adder, 14 is a second memory, 14
a is the output data of the same memory, 15 is the first memory, 15 is a shift register, 17 to 19 are amplifiers,
20 to 22 are output terminals, 23 is a television receiver, 2
4 is a display screen of the television receiver, 25a is a center adjustment point of the display screen, and 25b to 25f are peripheral adjustment points.

Claims

[Scope of utility model registration request]

In a grid or dot pattern adjustment signal generation circuit for convergence adjustment of a video display device that displays a color image, a display in which a count value of a clock signal corresponding to a display pixel is stored in advance in a first memory as an address signal. The pattern data is read out, converted into a serial signal, and supplied to the video signal output terminal, and the counted value of the carry signal of the address signal counter is used as an address signal of a second memory, and is stored in the same memory in advance. The start address data is read out for each scanning line of the first memory, and the clock signal is used as the offset data of the counted address signal, and a grating or dot pattern is formed at irregular intervals, coarse at the center of the display screen and dense at the periphery. A convergence adjustment signal generation circuit characterized by outputting a signal.