JPH0447513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an imaging device that can obtain high-quality images by combining a shutter and an imaging device.

In recent years, solid-state imaging devices such as CCD type and MOS type have been used in various fields.

Additionally, large-area solid-state imaging devices using amorphous silicon or the like have also been proposed.

These solid-state imaging devices can obtain appropriate image information corresponding to a subject by controlling the storage time of image information.

Electronic cameras using such solid-state image sensors are disclosed in, for example, Japanese Patent Application Laid-Open No. 1983-52912,
It is known from Japanese Patent Application Laid-open No. 140544/1983. However, the former invention has a structure in which the exposure time is variably adjusted by the shutter while the image sensor is storing data for a certain period of time, and has the drawback that image quality deteriorates due to dark current.

Further, in the latter invention, since images are accumulated only by controlling the accumulation time of the image sensor, there is a drawback that smear occurs during charge transfer.

It is an object of the present invention to provide an imaging device that can overcome these drawbacks of the prior art.

In addition, in order to achieve such an object, in the imaging device of the present invention, a shutter is provided in front of the imaging surface of the imaging element, and when the shutter is opened, the accumulation of images in the imaging element is started, and when the shutter is closed, the accumulation of images is started. The present invention is characterized in that it has a control means for controlling the storage to end when the storage is completed.

Thereby, dark current can be reduced to a minimum, and smear can also be effectively prevented.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a block diagram of a single-lens reflex camera to which an interchangeable video adapter can be attached as an embodiment of the present invention.

LS is the photographing lens, AS is the aperture, QM is the quick return mirror, FS is the focus plate, CL is the condenser lens, PR is the pentaprism, EL is the eyepiece lens, SP is the photoelectric conversion element for photometry, and MT is the current for exposure display. ST is the shutter, FP is the film positioning rail, and CT is the connection terminal on the camera side. The items described below constitute the replacement video adapter, where SM is the area type solid-state image sensor, DM is the drive circuit for the solid-state image sensor as a control means, AM is the replacement back cover, and CM is the replacement video adapter side. Connect terminal, CB1,
CB2 is the connection cable, CK1 is the video recording device,
CK2 is a display device such as a television receiver. still,
These adapter devices may be built into the camera. Alternatively, a package containing a built-in image sensor may be inserted into the focal plane instead of replacing the back cover. Rail surface for film position setting
Normally, a film is placed on the FP via a back cover with a film pressure plate (not shown), but in this figure, the solid-state image sensor SM of the replacement video adapter is placed on the focal plane, and the connect terminals CT and CM Via
Electrical information is transferred between the camera and the adapter. In this embodiment, a single-lens reflex camera is assumed, but the camera is not limited to this.

FIG. 2 is an example of an electric circuit of an embodiment of the imaging device of the present invention. The embodiment shown in this figure assumes a shutter-priority type single-lens reflex camera, where LM is a photometry circuit consisting of a photoelectric conversion element SP for photometry, an operational amplifier MP1 for photometry, and a logarithmic conversion element LD, and SV is a photometry circuit that This is an exposure information setting circuit for setting sensitivity information and TV shutter speed information.

The outputs of LM, TV, and SV are added by operational amplifier OP1, and aperture information is output, and the aperture display ammeter
The aperture is displayed on the MT, and the aperture control circuit
Aperture is set with magnet Mg1 via ASK.

The first press of the shutter release button (not shown) turns on the photometry power switch SW1, supplies power E1 to the photometry and display circuit system, and displays exposure information. Next, press the second shutter release button.
Press down to turn on the shooting power switch SW2,
Power is started to be supplied to the aperture and shutter speed control circuits.

Shutter time setting resistor V1 linked to shutter time setting means, second time integration capacitor C
1. The count switch SW5, which turns off almost at the same time as the shutter starts to open, the shutter trigger circuit SHT, the bias resistor R8, and the switching transistor Tr8 form a timer circuit for controlling the shutter time. When the aperture control is completed via magnet Mg1, the quick return mirror QM goes up, the shutter starts to open, SW5 turns off, and the time-setting control of the shutter control time-setting circuit starts, and when the potential of C1 reaches a certain value or more, Schmitt trigger circuit SHT is inverted, R8, Tr8
The shutter control magnet Mg2 is turned off via , the shutter closes, and exposure when using normal film is completed.

Next, transistors Tr1 to Tr4, resistors R1 to R
6. Switch SW6 that turns on when the shutter is fully open and turns off when the shutter is closed or wound, etc. Counter
CNT, magnitude comparator MCP, R-
S flip-flop RS1, AND gate AN1
The circuit consisting of the image capturing number setting circuit VST and the image capture number setting circuit VST is an example of a control circuit for effectively performing continuous image capturing when the replacement video adapter of this embodiment is attached.

The circuit consisting of the capacitor C2 and the resistor R7 is a power up clear circuit for initially resetting the counter CNT and flip-flop RS1 when the photographing power switch SW2 is turned on.

Camera, adapter and connection terminal CT1, CM
When connected through 1,..., CT5, CM5, transistor Tr2 is turned on by pull-down resistor R10 on the adapter side, transistor Tr1 is also turned on, and both terminals of _C1 are shorted, so it is synchronized with the start of opening of the shutter. and count switch
Even if SW5 is turned off, C1 is not charged. At the same time, the output of the AND gate AN1 becomes high level, so the transistor Tr4 is turned on via the resistor R4, and the shutter is prohibited from closing. In addition, transistor Tr3 is connected to resistors R5 and R6, and connect terminal CT.
5. Drive circuit DM of solid-state image sensor via CM5
A high level signal is supplied from the A3 terminal of the SM only while image information is being read from the SM.
Initially it is off.

When SW6 is turned on in conjunction with the full opening of the shutter, transistor Tr1 is turned off and time control of the shutter control time circuit is started, and A2 of the solid-state image pickup device drive circuit DM is connected via connection terminals CT4 and CM4. The terminal becomes low level, and the solid-state image sensor SM starts storing image information corresponding to the subject. When the potential of C1 exceeds a certain value, the Schmitt trigger circuit SHT is inverted, a pulse is generated at the A1 terminal of the solid-state image sensor drive circuit DM via the connection terminals CT3 and CM3, and image information is sent to the solid-state image sensor SM. When the video recording device CK1 starts magnetic recording,
The counter CNT counts the reversal of SHT, and compares it with the number of images preset by the photographer in the image capture number setting circuit VST via the magnitude comparator MCP. If the count number of CNT is smaller than the number set in VST, Since MCP does not produce a match signal,
The output of AN1 which is not set in RS1 also remains at high level, and the transistor is also kept in the on state via resistor R4, and the shutter control magnet is turned on.
Mg2 continues to be energized and prohibits the shutter from closing.

On the other hand, while the image information of SM is read out and recorded via CK1, in this embodiment, the drive circuit
Since the A3 terminal of the DM becomes high level, the transistor Tr3 is turned on via the connection terminals CM5 and CT5, the charge in C1 is discharged, and the shutter control time circuit is reset and the OR gate is activated.
The output of OR1 becomes high level, and unnecessary accumulated image information to the solid-state image sensor is reset.
All image information from SM is read out and CK1
When recording is completed, the A3 terminal of the DM becomes low level, transistor Tr3 is turned off, time control of the shutter control time circuit starts again, and the output of OR1 becomes low level, so the solid-state imaging is stopped. Accumulation of image information corresponding to the subject in the element SM is also started again.

When the time constant control of the shutter control time circuit ends, its output is inverted, and the accumulation of image information in the solid-state image sensor SM is completed, and the counter CNT is
Count SHT reversals and compare VST information with MCP.

When this sequence is repeated and the number of images set by the photographer on the VST matches the number of images counted on the counter CNT, the output of the magnitude comparator MCP goes high and the RS flip-flop RS1 is set, causing the output to go low. Since the output of AN1 becomes low level, the transistor Tr4 is turned off, Mg2 is turned off, the shutter is closed, and the connection terminal CT2,
An imaging end signal is transmitted to the video recording device CK1 via CM2.

Further, in the embodiment of the present invention, when using the conversion video adapter, the film sensitivity information on the camera side is switched to the sensitivity of the solid-state image sensor. That is, in Fig. 2, when the conversion video adapter is connected to the camera, the transistor TR1 is connected to the pull-down resistor R10 via the connection terminals CT1 and CM1.
5 turns on, transistor Tr16 turns on,
The transistor TR17 is turned off via the inverter IN, and the sensitivity information VS of the solid-state image sensor is input to the operational amplifier OP1 instead of the film sensitivity information SV.
An aperture suitable for the sensitivity of the solid-state image sensor is set.

In this embodiment, a shutter-priority type camera has been described, but it goes without saying that the present invention can be similarly applied to a shutter control time circuit of an aperture-priority type camera that controls the shutter speed based on a photometric calculation value. stomach. For example, when the present invention is applied to an aperture-priority memory-type electronic shutter camera to perform continuous imaging, the quick return mirror is raised and the photometric calculation value for controlling the shutter speed is memorized. Based on this, the storage time of the solid-state image sensor of the conversion adapter is continuously controlled via the shutter control time circuit, so it is possible to obtain appropriate image information corresponding to the subject in a short time. be. Further, although the shutter control time-setting circuit is illustrated as an analog one, the same applies to a digital time-setting circuit using a counter.

FIG. 3 shows a specific embodiment of a solid-state imaging device SM suitable for the present invention.

A ₁ …, An, …, Z ₁ …, Zn is a photosensitive pixel portion having a charge accumulation function, CA ₁ , …, CAn, … CZ ₁ , …,
CZn is an integral clear gate for clearing the charge accumulated in the photosensitive pixel portion, and is connected to OR1 and the output via the ICG terminal. FA1,…,FAn,
..., FZ ₁ , ...FZn are charge transfer gates for transferring image information stored in the photosensitive pixel portion corresponding to the subject to vertical analog shift registers VS ₁ , ...VSn for charge transfer. Connected to the DM's _A1 terminal via the SH terminal. HS is an analog shift register for horizontal charge transfer, and these vertical and horizontal shift registers are similar to those of DM.
Clock pulses generated from _A0 terminal group Vφ ₁ , Vφ ₂ ,
Driven by Hφ ₁ and Hφ ₂ . The image information transferred to the vertical shift register is transferred via a vertical shift register and a horizontal shift register in a known manner, and the image information transferred to the right end of the horizontal shift register is transferred to a field effect transistor (FET) FC.
1, FC2, and resistors R30 to R32, the voltage information is sequentially output from the VF terminal as voltage information.

As described above, according to the present invention, a shutter is provided in front of the imaging surface of the image sensor, and when the shutter is opened, the accumulation of images in the image sensor is started,
Since it has a control means that controls the accumulation to end when the shutter is closed, dark current can be reduced to a minimum, smear can also be effectively prevented, and high-quality still image signals can be obtained. There is an effect that can be done.

Further, according to the present invention, the shutter operation can be varied between continuous shooting mode and single shooting mode, thereby improving the functionality of a camera using an image sensor such as a CCD.

Furthermore, in particular, in continuous shooting mode, the imaging means is reset every time signal accumulation for one image is completed to discard unnecessary signal charges, so it is possible to obtain sharp captured images even in continuous shooting mode. can.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an example of the configuration of the camera of the present invention, FIG. 2 is a diagram showing an example of the electric circuit of the camera of the present invention, and FIG. 3 is a diagram showing an example of the configuration of an image sensor suitable for the present invention. FIG. ST...Shutter, SM...Image sensor, LM...
...Photometering circuit, ASK...Aperture control circuit, Mg2...
Shutter closing control magnet, CNT...counting circuit, UST...number of shots setting circuit, DM...imaging element drive circuit.

Claims (1)

[Scope of Claims] 1. It has a shutter that opens and closes the imaging optical system for each photograph, and a camera control means that drives and controls the shutter, and is configured so that it can be attached to a camera that can attach silver halide film. The imaging device includes an imaging means for converting an optical image via an imaging optical system of the camera into an electrical signal, in an exchangeable back cover unit of the camera, and an imaging means that is attached to the camera. is connected to the camera control means, and when in single-shot mode, the shutter immediately closes the imaging optical system after the accumulation of the image-taking means is completed, and when in continuous-shot mode, in which multiple images are taken continuously, continuous shooting is performed. An imaging apparatus comprising: control means for controlling the camera control means so as to prevent the shutter from closing the imaging optical system until the accumulation of the number of images is completed. 2. The imaging apparatus according to claim 1, wherein the control means resets the imaging means every time the accumulation of one image is completed in continuous shooting mode.