JPH044753U - - Google Patents
Info
- Publication number
- JPH044753U JPH044753U JP1990046148U JP4614890U JPH044753U JP H044753 U JPH044753 U JP H044753U JP 1990046148 U JP1990046148 U JP 1990046148U JP 4614890 U JP4614890 U JP 4614890U JP H044753 U JPH044753 U JP H044753U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- power
- ground
- hole
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
第１図および第２図は本考案の実施例を示し、
第１図は側断面図、第２図は平面図である。第３
図はＴＡＢ方式の半導体装置の一例を示す要部斜
視図、第４図は高周波測定に対応した半導体装置
の側断面図を示す。
３……半導体ペレツト、５……多層配線基板、
６……透孔、７ａ……接地パターン、７ｂ……電
源パターン、１０……導電パターン。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a side sectional view, and FIG. 2 is a plan view. Third
The figure is a perspective view of a main part of an example of a TAB type semiconductor device, and FIG. 4 is a side sectional view of a semiconductor device compatible with high frequency measurement. 3...Semiconductor pellet, 5...Multilayer wiring board,
6... Through hole, 7a... Ground pattern, 7b... Power supply pattern, 10... Conductive pattern.
Claims (1)
ンを形成した多層配線基板の表面に、上記接地パ
ターンと接続された接地ライン、電源パターンと
接続された電源ライン、マイクロストリツプライ
ンを含む信号ラインをそれぞれ構成する導電パタ
ーンをその一端を透孔内に延在させて形成し、透
孔内に配置した半導体ペレツトの電極と導電パタ
ーンとを接続したことを特徴とする半導体装置。 A signal line including a ground line connected to the ground pattern, a power line connected to the power pattern, and a microstrip line is provided on the surface of a multilayer wiring board that has through holes and has a ground pattern and a power pattern formed between the layers. 1. A semiconductor device characterized in that each of the conductive patterns is formed by extending one end thereof into a through hole, and the conductive pattern is connected to an electrode of a semiconductor pellet placed in the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046148U JPH044753U (en) | 1990-04-26 | 1990-04-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046148U JPH044753U (en) | 1990-04-26 | 1990-04-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044753U true JPH044753U (en) | 1992-01-16 |
Family
ID=31560972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990046148U Pending JPH044753U (en) | 1990-04-26 | 1990-04-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044753U (en) |
-
1990
- 1990-04-26 JP JP1990046148U patent/JPH044753U/ja active Pending