JPH0447718U - - Google Patents
Info
- Publication number
- JPH0447718U JPH0447718U JP9008090U JP9008090U JPH0447718U JP H0447718 U JPH0447718 U JP H0447718U JP 9008090 U JP9008090 U JP 9008090U JP 9008090 U JP9008090 U JP 9008090U JP H0447718 U JPH0447718 U JP H0447718U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- base
- emitter
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Control Of Electrical Variables (AREA)
Description
【図面の簡単な説明】
第1図は本考案の第1の実施例の回路図、第2
図は第1図の回路に使用された定電流回路の電圧
−電流特性図、第3図は本考案と従来例とを供給
電流について比較するための特性図、第4図は本
考案の第2の実施例の回路図、第5図は従来例の
回路図。
図中、TVは電源端子、TOUTは出力端子、
TGはアース端子。[Brief Description of the Drawings] Figure 1 is a circuit diagram of the first embodiment of the present invention;
The figure is a voltage-current characteristic diagram of the constant current circuit used in the circuit of Figure 1, Figure 3 is a characteristic diagram for comparing the supplied current between the present invention and the conventional example, and Figure 4 is the characteristic diagram of the constant current circuit of the present invention. 2 is a circuit diagram of the second embodiment, and FIG. 5 is a circuit diagram of a conventional example. In the figure, TV is the power supply terminal, TOUT is the output terminal,
TG is the ground terminal.
Claims (1)
なくとも3つの抵抗器とトランジスタとの直列接
続回路を接続し、前記3つの抵抗器のうちの1つ
の抵抗器の両端電圧を、2つの差動トランジスタ
を含む差動増幅器のそれぞれの入力に与えるよう
にしたバンドギヤツプツエナー回路とを有する基
準電圧回路において、前記電流供給部の構成を、
2つの抵抗器の直列回路とこれら2つの抵抗器の
接続点にベースを、前記直列回路の一端と電源ラ
インとの間にエミツタ、コレクタをそれぞれ接続
し、前記直列回路の他端をアースラインに接続し
た第1のトランジスタ回路と、前記電源ラインと
前記バンドギヤツプツエナー回路との間にコレク
タ、エミツタを接続すると共に、ベースを前記差
動増幅器の出力側に接続した第2のトランジスタ
回路と、前記直列回路の一端にベースを、前記電
源ラインには抵抗器を介してエミツタを、前記第
2のトランジスタのベースにコレクタをそれぞれ
接続した第3のトランジスタ回路とで構成したこ
とを特徴とする基準電圧回路。 (2) 電流供給部とこの電流供給部に対して少な
くとも1つの抵抗器とカレントミラー回路を構成
するための一方のトランジスタとの直列回路を接
続し、該一方のトランジスタのベース−エミツタ
間電圧と前記カレントミラー回路を構成するため
の他方のトランジスタのベース−エミツタ間電圧
との差電圧を増幅器の入力トランジスタの入力と
して与えるようにしたバンドギヤツプツエナー回
路とを有する基準電圧回路において、前記電流供
給部の構成を、2つの抵抗器の直列回路とこれら
2つの抵抗器の接続点にベースを、前記直列回路
の一端と電源ラインとの間にはエミツタ、コレク
タをそれぞれ接続し、前記直列回路の他端をアー
スラインに接続した第1のトランジスタ回路と、
前記電源ラインと前記バンドギヤツプツエナー回
路との間にコレクタ、エミツタを接続すると共に
、ベースを前記増幅器の出力側に接続した第2の
トランジスタ回路と、前記直列回路の一端にベー
スを、前記電源ラインには抵抗器を介してエミツ
タを、前記第2のトランジスタのベースにコレク
タをそれぞれ接続した第3のトランジスタ回路と
で構成したことを特徴とする基準電圧回路。[Claims for Utility Model Registration] (1) A current supply section, and a series connection circuit of at least three resistors and transistors connected to the current supply section, and a resistor of one of the three resistors. A reference voltage circuit having a bandgap amplifier circuit configured to apply a voltage across the device to each input of a differential amplifier including two differential transistors.
Connect a base to a series circuit of two resistors and a connection point between these two resistors, connect an emitter and a collector between one end of the series circuit and a power line, and connect the other end of the series circuit to a ground line. a second transistor circuit having a collector and an emitter connected between the power supply line and the bandgap amplifier circuit, and a base connected to the output side of the differential amplifier; , a third transistor circuit having a base connected to one end of the series circuit, an emitter connected to the power supply line via a resistor, and a collector connected to the base of the second transistor. Reference voltage circuit. (2) A current supply unit and a series circuit of at least one resistor and one transistor for forming a current mirror circuit are connected to the current supply unit, and the voltage between the base and emitter of the one transistor is In the reference voltage circuit, the reference voltage circuit includes a bandgap amplifier circuit configured to apply a voltage difference between the base-emitter voltage of the other transistor to form the current mirror circuit as an input to the input transistor of the amplifier. The supply section has a configuration in which a series circuit of two resistors is connected, a base is connected to a connection point between these two resistors, an emitter and a collector are connected between one end of the series circuit and the power supply line, and the series circuit is connected to the base. a first transistor circuit whose other end is connected to a ground line;
a second transistor circuit whose collector and emitter are connected between the power supply line and the bandgap amplifier circuit, and whose base is connected to the output side of the amplifier; 1. A reference voltage circuit comprising: a power supply line connected to an emitter via a resistor; and a third transistor circuit having a collector connected to the base of the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9008090U JP2534224Y2 (en) | 1990-08-30 | 1990-08-30 | Reference voltage circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9008090U JP2534224Y2 (en) | 1990-08-30 | 1990-08-30 | Reference voltage circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0447718U true JPH0447718U (en) | 1992-04-23 |
| JP2534224Y2 JP2534224Y2 (en) | 1997-04-30 |
Family
ID=31824522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9008090U Expired - Lifetime JP2534224Y2 (en) | 1990-08-30 | 1990-08-30 | Reference voltage circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2534224Y2 (en) |
-
1990
- 1990-08-30 JP JP9008090U patent/JP2534224Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2534224Y2 (en) | 1997-04-30 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |