JPH0447765U - - Google Patents

Info

Publication number
JPH0447765U
JPH0447765U JP9084590U JP9084590U JPH0447765U JP H0447765 U JPH0447765 U JP H0447765U JP 9084590 U JP9084590 U JP 9084590U JP 9084590 U JP9084590 U JP 9084590U JP H0447765 U JPH0447765 U JP H0447765U
Authority
JP
Japan
Prior art keywords
power supply
output circuit
microcomputer
eprom
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9084590U
Other languages
Japanese (ja)
Other versions
JPH0749554Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990090845U priority Critical patent/JPH0749554Y2/en
Publication of JPH0447765U publication Critical patent/JPH0447765U/ja
Application granted granted Critical
Publication of JPH0749554Y2 publication Critical patent/JPH0749554Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Power Sources (AREA)
  • Microcomputers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は、本考案の一実施例を示す回路図である
。 ４……インバータ、７……ＥＰＲＯＭ、８……
電源端子、９……レベルシフト回路。 The drawing is a circuit diagram showing an embodiment of the present invention. 4...Inverter, 7...EPROM, 8...
Power supply terminal, 9...Level shift circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 所定ビツトデータの書き込み／読み出しが
行われるＥＰＲＯＭと、所定ビツトデータを出力
する出力回路と、を内蔵したマイクロコンピユー
タにおいて、 前記ＥＰＲＯＭの書き込み電圧が印加される電
源端子と、前記出力回路の電源電圧が印加される
電源端子と、を共用したことを特徴とするマイク
ロコンピユータ。 (2) 前記ＥＰＲＯＭの書き込み電圧は、前記出
力回路の電源電圧より大であることを特徴とする
請求項(1)記載のマイクロコンピユータ。 (3) 前記出力回路は、ＣＭＯＳトランジスタと
、該ＣＭＯＳトランジスタ内のＰＭＯＳトランジ
スタのゲート電圧を電源端子の印加状態に応じて
レベルシフトするレベルシフト回路と、を備えて
成ることを特徴とする請求項(2)記載のマイクロ
コンピユータ。[Claims for Utility Model Registration] (1) In a microcomputer that includes an EPROM in which predetermined bit data is written/read and an output circuit that outputs predetermined bit data, a write voltage for the EPROM is applied. A microcomputer characterized in that a power supply terminal and a power supply terminal to which a power supply voltage of the output circuit is applied are shared. (2) The microcomputer according to claim 1, wherein the write voltage of the EPROM is higher than the power supply voltage of the output circuit. (3) The output circuit includes a CMOS transistor and a level shift circuit that level-shifts the gate voltage of a PMOS transistor in the CMOS transistor according to the applied state of a power supply terminal. (2) The microcomputer described.
JP1990090845U 1990-08-29 1990-08-29 Microcomputer Expired - Lifetime JPH0749554Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990090845U JPH0749554Y2 (en) 1990-08-29 1990-08-29 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990090845U JPH0749554Y2 (en) 1990-08-29 1990-08-29 Microcomputer

Publications (2)

Publication Number Publication Date
JPH0447765U true JPH0447765U (en) 1992-04-23
JPH0749554Y2 JPH0749554Y2 (en) 1995-11-13

Family

ID=31825936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990090845U Expired - Lifetime JPH0749554Y2 (en) 1990-08-29 1990-08-29 Microcomputer

Country Status (1)

Country Link
JP (1) JPH0749554Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6419593A (en) * 1987-07-14 1989-01-23 Toshiba Corp Programmable rom

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6419593A (en) * 1987-07-14 1989-01-23 Toshiba Corp Programmable rom

Also Published As

Publication number Publication date
JPH0749554Y2 (en) 1995-11-13

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