JPH0447766U - - Google Patents
Info
- Publication number
- JPH0447766U JPH0447766U JP8991890U JP8991890U JPH0447766U JP H0447766 U JPH0447766 U JP H0447766U JP 8991890 U JP8991890 U JP 8991890U JP 8991890 U JP8991890 U JP 8991890U JP H0447766 U JPH0447766 U JP H0447766U
- Authority
- JP
- Japan
- Prior art keywords
- current
- mirror circuit
- current mirror
- power supply
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000470 constituent Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Description
第1図は本考案の第1の実施例のブロツク図、
第2図は本考案の第2の実施例の回路図、第3図
は従来の絶対値回路の回路図とその入出力特性の
図である。
1……基準電源、2……第1カレントミラー回
路、3……第2カレントミラー回路、4……第3
カレントミラー回路、5……第4カレントミラー
回路、6……第5カレントミラー回路、7……第
6カレントミラー回路、8……第7カレントミラ
ー回路、RB,Rr,Rin……抵抗、RO……
出力抵抗。
FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional absolute value circuit and its input/output characteristics. 1... Reference power supply, 2... First current mirror circuit, 3... Second current mirror circuit, 4... Third
Current mirror circuit, 5...Fourth current mirror circuit, 6...Fifth current mirror circuit, 7...Sixth current mirror circuit, 8...Seventh current mirror circuit, RB, R r , R in ... Resistor ,RO...
Output resistance.
Claims (1)
を2等分する2個の抵抗Rrと、 前記基準電源1に接続され、前記基準電圧を2
等分すると共に直列に入力交流電源Vinが接続
されている2個の抵抗Rinと、 各回路に電流を供給する直流電源Vccに直列
に抵抗RBを挟んで接続される素子を含む少なく
とも3個の素子で構成される第1のカレントミラ
ー回路2と、 前記抵抗RBに接続されている素子を除く前記
第1のカレントミラー回路2を構成する素子にそ
れぞれその構成素子が直列に接続されており、入
力交流電源Vinの負のサイクルに一方の構成素
子のコレクタ電流が増加する第3のカレントミラ
ー回路4と、 前記直流電源Vccに直列に前記抵抗RBを挟
んで接続される素子を含む少なくとも3個の素子
で構成される第2のカレントミラー回路3と、 前記抵抗RBに接続されている素子を除く前記
第2のカレントミラー回路3を構成する素子と、
前記第3のカレントミラー回路4を構成する素子
との間にそれぞれその構成素子が接続されており
、入力交流電源Vinの正のサイクルに一方の構
成素子のコレクタ電流が増加する第4のカレント
ミラー回路5と、 前記入力交流電流Vinの負のサイクルに前記
第2のカレントミラー回路3の構成素子のコレク
タ電流の増加分だけの電流を一方の素子に流し、
他方の素子にその増加分の電流を出力する第5の
カレントミラー回路6と、 前記入力交流電源Vinの正のサイクルに前記
第4のカレントミラー回路5の構成素子のコレク
タ電流の増加分だけの電流を一方の素子に流し、
他方の素子にその増加分を出力する第6のカレン
トミラー回路7と、 該第6のカレントミラー回路7の出力電流に基
づいて前記コレクタ電流の増加分の電流を出力す
る第7のカレントミラー回路8と、 前記入力交流電源Vinの負のサイクルに第5
のカレントミラー回路6の出力電流が流され、正
のサイクルに第7のカレントミラー回路8の出力
電流が流され、前記入力交流電源Vinの出力電
圧の絶対値電圧を出力する出力抵抗ROとを具備
することを特徴とする絶対値回路。[Claims for Utility Model Registration] A reference power source 1 having a constant reference voltage, two resistors R r connected in parallel to the reference power source 1 and dividing the reference voltage into two equal parts, and the reference power source 1 connected, the reference voltage is 2
At least two resistors R in which are divided equally and are connected in series with the input AC power supply V in, and an element which is connected in series with the DC power supply V cc that supplies current to each circuit with a resistor RB in between. A first current mirror circuit 2 composed of three elements, each of which is connected in series to each element constituting the first current mirror circuit 2 except for the element connected to the resistor RB. a third current mirror circuit 4 in which the collector current of one component increases during a negative cycle of the input AC power supply V in ; and an element connected in series to the DC power supply V cc with the resistor RB in between. a second current mirror circuit 3 made up of at least three elements including: an element constituting the second current mirror circuit 3 excluding the element connected to the resistor RB;
Each component is connected between the elements constituting the third current mirror circuit 4, and the collector current of one component increases in a positive cycle of the input AC power supply V in . a mirror circuit 5; a current corresponding to an increase in the collector current of the constituent elements of the second current mirror circuit 3 is caused to flow through one element during a negative cycle of the input AC current V in ;
a fifth current mirror circuit 6 that outputs the increased current to the other element; and a fifth current mirror circuit 6 that outputs the increased current to the other element; and a fifth current mirror circuit 6 that outputs the increased amount of current to the other element; A current of is passed through one element,
a sixth current mirror circuit 7 that outputs the increased amount to the other element; and a seventh current mirror circuit that outputs the increased amount of the collector current based on the output current of the sixth current mirror circuit 7. 8, and a fifth in the negative cycle of the input AC power supply V in
The output current of the seventh current mirror circuit 6 is passed in the positive cycle, and the output current of the seventh current mirror circuit 8 is passed in the positive cycle, and the output resistor RO outputs the absolute value voltage of the output voltage of the input AC power supply V in . An absolute value circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8991890U JP2515229Y2 (en) | 1990-08-28 | 1990-08-28 | Absolute value circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8991890U JP2515229Y2 (en) | 1990-08-28 | 1990-08-28 | Absolute value circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0447766U true JPH0447766U (en) | 1992-04-23 |
| JP2515229Y2 JP2515229Y2 (en) | 1996-10-30 |
Family
ID=31824242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8991890U Expired - Lifetime JP2515229Y2 (en) | 1990-08-28 | 1990-08-28 | Absolute value circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515229Y2 (en) |
-
1990
- 1990-08-28 JP JP8991890U patent/JP2515229Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2515229Y2 (en) | 1996-10-30 |